6402 datasheet(234/250 Pages) INTEL

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Registers

234

Intel® 6400/6402 Advanced Memory Buffer Datasheet

14.8.2.5

SBFIBRXMSK: SB Intel IBIST Receiver Mask Register

This register enables Intel IBIST operations for individual lanes. This mask only applies

to receivers and not transmitters.

14.8.2.6

SBFIBTXSHFT: SB Intel IBIST Transmitter Inversion Shift Register

Each bit in this register enables inverting the patterns that is driven on corresponding

lanes. If AUTOINVSWPEN bit is set in port control register, the TXINVSHFT field is

rotated left at the completion of each pattern buffer set.

14.8.2.7

SBFIBRXSHFT: SB Intel IBIST Receiver Inversion Shift Register

Each bit in this register enables inverting the patterns that is received on corresponding

lanes. If AUTOINVSWPEN bit is set in port control register, the RXINVSHFT field is

rotated left at the completion of each pattern buffer set.

14.8.2.8

SBFIBRXLNERR: SB Intel IBIST Receiver Lane Error Status

This records the error status from each lane.

Device:

NodeID

Function: 6

Offset:

90h

Bit

Attr

Default

Description

31:10

000000h

Reserved

9:0

RWST

3FFh

RXMASK: Selects which channels to enable for testing.

Device:

NodeID

Function: 6

Offset:

94h

Bit

Attr

Default

Description

31:10

000000h

Reserved

9:0

RWST

3FFh

TXINVSHFT: Transmitter Inversion Shift Register.

Device:

NodeID

Function: 6

Offset:

98h

Bit

Attr

Default

Description

31:10

000000h

Reserved

9:0

RWST

3FFh

RXINVSHFT: Receiver Inversion Shift Register.

Device:

NodeID

Function: 6

Offset:

9Ch

Bit

Attr

Default

Description

31:10

000000h

Reserved

9:0

ROST

000h

RXERRSTAT: Receiver Error Status

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