6402 datasheet(50/250 Pages) INTEL

50 / 250 page

Electrical, Power, and Thermal

Intel® 6400/6402 Advanced Memory Buffer Datasheet

4.4.11

Advance Memory Buffer Component Electrical Timing

Summary

Table 4-8 and Table 4-9 contain the electrical timing specifications for the Advance

Memory Buffer component DDR2 interface.

Table 4-8.

Advance Memory Buffer Component DDR2 Electrical Timing Specifications

Symbol

Parameter

DDR2 667

DDR2 533

Unit

Fig #

Min

Max

Min

Max

System Memory Clock Timings

tCK

Ideal clock (CK) period

3.0

3.75

tCH

CK high time

1.35

1.70

tCL

CK low time

1.35

1.70

tjit

CK cycle to cycle Jitter

150

175

4-7

tjitHP

CK half-cycle jitter

150

175

4-7

TDQSCK

Clock rising edge to DQS

rising edge, or clock falling

edge to DQS falling edge --

includes -110/-70 ps for

package

-200

-210

4-10

System Memory Address/Command/Control Signal Timings (Normal)

tCVB

CMD/ADD/CNTL output valid

before CLK/CLK

1260

1615

4-8

tCVA

CMD/ADD/CNTL output valid

after CLK/CLK -- includes

-140 ps for package

1120

1475

4-8

System Memory Address/Command/Control Signal Timings (Early)

tECVB

Early CMD/ADD/CNTL output

valid before CLK/CLK

1760

2240

4-9

tECVA

Early CMD/ADD/CNTL output

valid after CLK/CLK --

includes -140 ps for package

620

850

4-9

System Memory Data and Strobe Signal Timings

tDVB

DQ[63:0], CB[7:0], valid

before DQS[15:0]/

DQS[15:0] crossing

575

750

4-6

tDVA

DQ[63:0], CB[7:0], valid

after DQS[15:0]/DQS[15:0]

crossing

575

750

4-6

tDOPW

DQ[63:0]. CB[7:0] Output

Valid Pulse Width

1.35

1.70

tSUAMB

DQ and CB Input Setup Time

to DQS Crossing

-530

-700

4-11

tHDAMB

DQ and CB Input Hold Time

After DQS Crossing

970

1180

4-11

tWPREAMB

DQS Write Preamble

Duration

2.85

3.5

3.58

4.25

4-12

tWPSTAMB

DQS Write Postamble

Duration

1.35

1.65

1.7

2.05

4-13

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