6402 datasheet(11/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

Introduction

This document is a core specification for a Fully Buffered DIMM (FB DIMM, also FBD)

memory system. This document, along with the other core specifications, must be

treated as a whole. Information critical to an Intel® 6400/6402 Advanced Memory

Buffer (AMB) design appears in the other specifications, with specific cross-references

provided.

1.1

Intel® 6400/6402 Advanced Memory Buffer

Overview

The Intel 6400/6402 Advanced Memory Buffer (AMB) complies with the FB-DIMM

Architecture and Protocol Specification. This device supports DDR2 SDRAM memory

components. The AMB allows buffering of memory traffic to support large memory

capacities. All memory control for the DRAM devices resides in the host, including

memory request initiation, timing, refresh, scrubbing, sparing, configuration access,

and power management. The AMB interface is responsible for handling FBD channel

and memory requests to and from the local DIMM and for forwarding requests to other

DIMMs on the FBD channel.

Fully Buffered DIMM (FBD) provides a high memory bandwidth, large capacity channel

solution that has a narrow host interface. Fully Buffered DIMMs use commodity DRAMs

isolated from the channel behind a buffer on the DIMM. The memory capacity is 288

devices per channel and total memory capacity scales with DRAM bit density.

The AMB will perform the following FBD channel functions:

• Supports channel initialization procedures as defined in the initialization chapter of

the FB-DIMM Architecture and Protocol Specification to align the clocks and the

frame boundaries, verify channel connectivity, and identify AMB DIMM position.

• Supports the forwarding of southbound and northbound frames, servicing requests

directed to a specific AMB or DIMM, as defined in the protocol chapter, and merging

the return data into the northbound frames.

• If the AMB resides on the last DIMM in the channel, the AMB initializes northbound

frames.

• Detects errors on the channel and reports them to the host memory controller.

• Support the FBD configuration register set as defined in the register chapters.

• Acts as DRAM memory buffer for all read, write, and configuration accesses

addressed to the DIMM.

• Provides a read buffer FIFO and a write buffer FIFO.

• Supports an SMBus protocol interface for access to the AMB configuration registers.

• Provides logic to support MemBIST and IBIST Design for Test (DFx) functions.

• Provides a register interface for the thermal sensor and status indicator.

• Functions as a repeater to extend the maximum length of FBD Links.

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