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6402 bảng dữ liệu(PDF) 56 Page - Intel Corporation |
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6402 bảng dữ liệu(HTML) 56 Page - Intel Corporation |
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56 / 250 page ![]() Debug and Logic Analyzer Mode 56 Intel® 6400/6402 Advanced Memory Buffer Datasheet 5.1.4 LAI Mode Signal Definitions Table 5-1. DDR Pins Shared With LAI Functionality Signal Type Count Speed (MHz) Use in LAI Mode Comment DDR DDR DQ & DQS 108 533/667 ~ LAI signal DQS must run single ended in LAI mode DDR Cmd/Addr 56 266/333 ~ LAI signal Most must run double speed in LAI mode Some may be dedicated to bidirectional Event Bus Clocks to DRAMs 8 533/667 ~ LAI signal May run single ended in LAI mode DDR Comp and analog 5 analog Not suitable for LAI signals Total DDR Pins 177 Table 5-2. List of Pins Required to Enable Debug With LAI Functionality Signal Type Count Speed (MHz) Comment Southbound S[59:0] 60 533/667 Data Northbound N[83:0] 84 533/667 Data MODE 1 267/333 TRIG[10:0] 11 267/333 CLK 4 267/333 Two Differential pairs QUAL 1 533/667 FRAME 1 533/667 EV[3:0] 4 100 Bidirectional Comp Pins 5 Analog Required for signal integrity Total Pins 171 Table 5-3. LAI Mode Added Signals (Sheet 1 of 2) Signal Type Direction Definition S[59:0] Out Southbound demuxed (6x10) traffic N[83:0] Out Northbound demuxed (6x14) traffic MODE Out Link mode: 0 = after training complete 1 = before training complete TRIG[10:0] Out Triggers to LA. This provides eleven unique trigger signals to the LA from the AMB LAI as a result of frame pattern matching, state matching, and/or cross-triggering events from other LAIs. This allows cooperating AMB LAIs to overcome (a) limitations of LA in recognizing serial traffic patterns that exceed LA pattern matching capabilities and, (b) relatively long latencies in cross- triggering between LA modules. |
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