6402 datasheet(95/250 Pages) INTEL

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Intel® 6400/6402 Advanced Memory Buffer Datasheet

Reset

9.4.2.1

Implementation Detail

1. The RESET# pad starts out low. This asynchronously asserts all internal resets.

2. After power comes up and REFCLK stabilizes, the PLLs start generating clocks. At

this time, the phase relations between the clocks are not guarantied to be correct.

3. RESET# rises. A synchronized version releases the reset on the logic running on

REFCLK. The chip monitors RESET# for 100 and 200 usec RESET# must remain

stable during this time. If it falls the wait starts again until a stable high occurs.

4. After a stable RESET# high is detected, the PLL is reset to bring the generated

clocks into correct alignment with themselves.

5. At this point the chip waits for the PLL to indicate reset complete. When it does, the

internal resets are deasserted for all clock domains except TCK.

9.4.3

Reset Sequence for a Fast Reset

Figure 9-1 below shows a fast reset sequence. Important steps are described below:

• The chip is running with the RESET# high and a full link initialization sequence has

been completed at least once.

• A electrical idle is detected on the primary Southbound FBD Link.

• If not the last DIMM, forward electrical idle Southbound to the next DIMM.

• Drive logic “0’s” on Northbound transmitters.

• The AMB completes the fast reset handshake (see below).

• Reset is asserted for all non-sticky registers.

• The values in the next fields are transferred to the Current fields.

• The PLL remains in lock but the clock outputs are reset, causing them to realign.

• IF not the last DIMM, the AMB waits for an electrical idle to appear on the

secondary Northbound FBD link.

• Forward electrical idle Northbound

• The chip is released from reset.

• Freezing sticky configuration registers through reset

9.4.4

Fast Reset Handshake

When a reset event is detected on the primary Southbound FBD link, the AMB does the

following:

• Immediately stops accepting new DRAM commands from the link.

• Halts all on-chip algorithms, including DRAM cal and MemBIST.

• Waits 200 ns for any in-process DRAM commands to complete.

• Asserts CKE high.

• Waits 200 ns for DRAM self-refresh exit to complete.

• Sends a DRAM precharge all to all ranks.

• Waits 30 ns for precharge all to complete.

• Sends DRAM self-refresh entry commands to all ranks

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