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6402 bảng dữ liệu(PDF) 44 Page - Intel Corporation

tên linh kiện 6402
Giải thích chi tiết về linh kiện  Advanced Memory Buffer
PDF  250 Pages
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Trang chủ  http://www.intel.com
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6402 bảng dữ liệu(HTML) 44 Page - Intel Corporation

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Electrical, Power, and Thermal
44
Intel® 6400/6402 Advanced Memory Buffer Datasheet
4.2
FB-DIMM Electrical Timing Specifications
The FB-DIMM Channel link electrical interface is more completely described in the High
Speed Differential Point-to-Point Link at 1.5V for Fully Buffered DIMM specification.
Refer to this document for recommended operating conditions.
Table 4-5 contains the FB-DIMM electrical timing specifications.
Notes:
1.
Defined in FB-DIMM Architecture and Protocol Spec
2.
Clocks defined as core clocks = 2x SCLK input
Note:
1.
tRESAMPLE is the delay from the southbound input to the southbound output, or the northbound input to
the northbound output when in resample mode, measured from the center of the data eye.
2.
tRESYNC is the delay from the southbound input to the southbound output, or the northbound input to the
northbound output when in resync mode, measured from the center of the data eye.
.
Table 4-5.
AMB FB-DIMM Timing/Electrical
Symbol
Parameter
Units
Min
Typ
Max
Notes
tEI Propagate
EI Assertion Pass-Thru Timing
clks
4
tEID
EI Deassertion Pass-Thru Timing
clks
tBitLock
tEI
EI Assertion Duration
clks
100
1
tBitLock
Bit Lock Interval
frames
119
1
tFrameLock
Frame Lock Interval
frames
154
1
Table 4-6.
AMB FB-DIMM Latency
Symbol
Parameter
Date
Rate
Min
Max
Units
Comments
tC2D_AMB
CMD2DATA = 0x36
CMD2DATA = 0x40
533
18.7
22.3
nS
667
16.2
19
nS
tC2D_AMB
CMD2DATA = 0x40
CMD2DATA = 0x46
533
20.5
24.2
nS
667
17.7
20.5
nS
CMD2DATA
R/C B
R/C B
533
0x36
0x48
nS
667
0x40
0x50
nS
tRESAMPLE
Resample Delay
533
0.9
1.6
nS
1
667
0.9
1.4
nS
1
tRESYNC
Resync Delay
533
2.3
3.9
nS
2
667
2
3.2
nS
2
Figure 4-1. Latency Timing Diagrams
0
2
13
4
6
57
8
10
911
11
tRESAMPLE
tRESYNC
0
2
13
4
6
57
8
10
911
11
Receiver Input
Transmit Output



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