6402 datasheet(58/250 Pages) INTEL

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Debug and Logic Analyzer Mode

Intel® 6400/6402 Advanced Memory Buffer Datasheet

5.1.6

FBD to LAI Signal Mapping

The following example show how an FBD Southbound Command Frame is transferred

from FBD frame format to LA Interface early/late data.

The LAI interface delays the SB “A slot” by one clock to capture the FBD frame in the

same “ABC” slot format that is sent from the host - rather than the “BCA” (B and C slots

from host frame N-1 plus A slot from host frame N) used by the normal mode AMBs to

minimize latency on the decode of slot A commands.

A[5:0]A

533/667

nbframe_data0[5:0],

[11:6]

5:0 captured on rising

edge of CLK,

11:6 captured on falling

edge of CLK

A[11:6]A

533/667

nbframe_data1[5:0],

[11:6]

BA[1:0]A,

A[15:12]A

533/667

nbframe_data2[5:0],

[11:6]

DQ[23:20], DQS[11],

DQS[11]

533/667

nbframe_data3[5:0],

[11:6]

DQ[31:28], DQS[12],

DQS[12]

533/667

nbframe_data4[5:0],

[11:6]

DQ[19:16], DQS[2],

DQS[2]]

533/667

nbframe_data5[5:0],

[11:6]

DQ[27:24], DQS[3],

DQS[3]

533/667

nbframe_data6[5:0],

[11:6]

DQ[15:12], DQS[10],

DQS[10]

533/667

nbframe_data7[5:0],

[11:6]

DQ[7:4], DQS[9],

DQS[9]

533/667

nbframe_data8[5:0],

[11:6]

DQ[11:8], DQS[1],

DQS[1]

533/667

nbframe_data9[5:0],

[11:6]

DQ[3:0], DQS[0],

DQS[0]

533/667

nbframe_data10[5:0],

[11:6]

CB[3:0], DQS[8],

DQS[8]

533/667

nbframe_data11[5:0],

[11:6]

CB[7:4], DQS[17],

DQS[17]

533/667

nbframe_data12[5:0],

[11:6]

DQ[63:60], DQS[16],

DQS[16]

533/667

nbframe_data13[5:0],

[11:6]

CLK[3:2]

267/333 MHz

Not supported in LAI

Mode

CLK[3:2]

267/333 MHz

Not supported in LAI

Mode

CLK[1:0]

267/333 MHz

LAI clock p [1:0]

CLK[1:0]#

267/333 MHz

LAI clock n [1:0]

Total DDR Pins

162

No spare pins

Table 5-4.

List of Shared DDR/LAI Pins (Sheet 2 of 2)

DDR Pin

Count

Speed Mbit/sec

LAI Mode

Comment

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