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Intel® 6400/6402 Advanced Memory Buffer Datasheet

FBD Channel Interface

DIMM and any set-up and hold-times in the AMB and the

DRAMs.

TDimm_Data_Delay

This includes the routing delays for the data and strobes from

the DRAM to the AMB, skews between the DRAMs, delays

through the DDR I/O cluster and any set-up and hold-times in

the AMB and DRAMs.

TCMD_To_Data

This is equal to (TRead_Latency + TAMB_Cmd_Delay +

TDimm_Cmd_Delay + TDimm_Data_Delay + TAMB_Data_Delay). This can

be specified with 1UI granularity. This will be different for each

DRAM type. It does not include any delays inside the I/O to

deskew and frame align the incoming data on the SB side nor

does it include the delays inside the NB I/O on the transmit side.

The TCAS and TAdditive_Latency are specified in the DRC register (DRC.cl and DRC.al). The

CMD2DATANXT register is initialized with a value equal to (TCMD_To_Data - TRead_Latency).

This value of CMD2DATANXT is specified in the SPD EEPROM. All AMBs are expected to

receive the data from the DRAMs with the calculated value of TCMD_To_Data.

All AMBs power up with a default value of 5 for TCMD_To_Data. This can be done either by

setting the default values of DRC.CL and DRC.AL or by setting the default value of the

CMD2DATACUR.FRMS to be 5. The AMBs must be able to return status and

configuration register reads with this default timing. This will enable the BIOS to

initialize the proper values from SPD.

The following simplified timing diagram illustrates how the last AMB uses the values

specified in DRC.CL, DRC.AL, CMD2DATANXT.DLYFRMS and CMD2DATANXT.DLYFRAC.

In Figure 2-2, it is assumed that there are no routing delays on the DIMM itself. The

command takes 10UI to get from SB FBD to the DDR I/O (TAMB_Cmd_Delay). This

includes time it takes to validate CRC of the frame and to decode the command. It is

assumed DDR_IO_Cmd_Clk shown in is delayed from the SB_Frame_Clk by 10 UI. The

Figure 2-2. Command to Data Delay Timing

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