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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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6402 bảng dữ liệu(PDF) 19 Page - Intel Corporation |
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6402 bảng dữ liệu(HTML) 19 Page - Intel Corporation |
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19 / 250 page  Intel® 6400/6402 Advanced Memory Buffer Datasheet 19 FBD Channel Interface 2.3.4 Address Mapping of DDR Commands to DRAMs 2.3.5 FBD L0s State The L0s state is not supported in the AMB. 2.4 Reliability, Availability, and Serviceability Refer to Chapter 5, “Reliability, Availability and Serviceability” in the FB DIMM Architecture and Protocol Specification [1] for FBD RAS requirements. 2.4.1 Channel Error Detection and Logging See for details on the error handling. 2.5 Channel Configuration 2.5.1 Re-sync and Resample Modes A separate control is available for both the NB and SB FBD links to select between lower latency re-sample and lower jitter re-sync modes for repeating received data. Selection between these two modes is a function of platform design and configuration and should be set by BIOS prior to link initialization The FBDSBCFGNXT.SBRESYNCEN and FBDNBCFGNXT.NBRESYNCEN bits make this selection. Descriptions of these two modes follows. 2.5.1.1 Accumulated Tracking Effects (Re-Sample Option) Each AMB acts as a repeater for the FBD channel. Since the data driven from each DIMM to the next DIMM may experience random or periodic phase shifts, the effect of these phase shifts must be accommodated in the design. Consider a system with three DIMMs daisy-chained together. A phase shift generated in the first DIMM will be seen by the second DIMM but will not be immediately propagated to the third DIMM. Unlike an analog buffer, the phase shift is not automatically driven to subsequent DIMMs since DDR2 x4 Config 20 19 18 17 16 15 14 13 12 11 10 98 765 4321 0 256Mb (64Mbx4) Row 1 X X RS X X B1 B0 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 1KB page Col 0 1 r/w RS X X B1 B0 X A 11 AP A9 A 8 A7 A6 A5 A 4 A3 A2 A 1 A 0 512Mb (128Mbx4) Row 1 X X RS A 13 X B1 B0 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 1KB page Col 0 1 r/w RS X X B1 B0 X A 11 AP A9 A 8 A7 A6 A5 A 4 A3 A2 A 1 A 0 1Gb (256Mbx4) Row 1 X X RS A 13 B2 B1 B0 A 12 A11 A 10 A9 A 8 A7 A6 A5 A 4 A3 A2 A 1 A 0 1KB page Col 0 1 r/w RS X B2 B1 B0 X A 11 A P A 9A 8A 7A 6A 5A 4A 3A 2A 1 A 0 2Gb (512Mbx4) Row 1 X A 14 RS A 13 B2 B1 B0 A 12 A11 A 10 A9 A 8 A7 A6 A5 A 4 A3 A2 A 1 A 0 1KB page Col 0 1 r/w RS X B2 B1 B0 X A 11 A P A 9A 8A 7A 6A 5A 4A 3A 2A 1 A 0 DDR2 x8 Config 20 19 18 17 16 15 14 13 12 11 10 98 765 4321 0 256Mb (32Mbx8) Row 1 X X RS X X B1 B0 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 1KB page Col 0 1 r/w RS X X B1 B0 X X AP A9 A 8 A7 A6 A5 A 4 A3 A2 A 1 A 0 512Mb (64Mbx8) Row 1 X X RS A 13 X B1 B0 A 12 A 11 A 10 A 9 A 8 A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0 1KB page Col 0 1 r/w RS X X B1 B0 X X AP A9 A 8 A7 A6 A5 A 4 A3 A2 A 1 A 0 1Gb (128Mbx8) Row 1 X X RS A 13 B2 B1 B0 A 12 A11 A 10 A9 A 8 A7 A6 A5 A 4 A3 A2 A 1 A 0 1KB page Col 0 1 r/w RS X B2 B1 B0 X X A P A 9A 8A 7A 6A 5A 4A 3A 2A 1 A 0 2Gb (256Mbx8) Row 1 X A 14 RS A 13 B2 B1 B0 A 12 A11 A 10 A9 A 8 A7 A6 A5 A 4 A3 A2 A 1 A 0 |
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