6402 datasheet(104/250 Pages) INTEL

104 / 250 page

Transparent Mode

104

Intel® 6400/6402 Advanced Memory Buffer Datasheet

10.2.3.3

Read Timing

Figure 10-3 shows read timing with the tester set to RL=3 and RL=5. Due to

complexities in the handling of read data in an AMB there is a latency of several cycles

from the TDRV pulse to TDQ and test status outputs. Specifically there is a constant

latency of four cycles plus the programmed CMD2DATA value from TDRV to TDQ (8

cycles total using the AMB settings above) and one cycle from TDQ to DRAM DQ. An

AMB may support shorter latencies but this is not required.

TCMP is latched on the rising edge of core clock. This initiates the read inside the AMB.

In most cases the AMB will latch DRAM read data slightly before TDQ data is needed.

The reason is most AMBs will load DDR data into a queue in the DRAM domain and

unload the data on a core clock edge. TDQ is typically not needed until the DRAM data

is in the core. The comparison of actual and expected data and propagation back to the

tester will occur on the next core clock edge.

The timings below are for BL=4. When testing BL=8 the TCMP pulse should be 3 clocks

wide rather than 1. Tester DQ data, DRAM data and the status outputs will be extended

appropriately to cover the burst length.

Figure 10-2. Transparent Mode Write Timing

6402 bảng dữ liệu(PDF) 104 Page - Intel Corporation