6402 datasheet(103/250 Pages) INTEL

103 / 250 page

Intel® 6400/6402 Advanced Memory Buffer Datasheet

103

Transparent Mode

Timing may be changed on the fly (for example, in the middle of a test pattern) by

changing the placement of edges from the tester. DRAM mode registers can be

programmed on the fly as needed by including (E)MRS commands in the tester data

stream. There is no need to change AMB settings during a test. The only exception is

that DRAM BL may be changed on the fly but the data logging logic may get confused if

DRAM BL does not match the BL expected by the data logger. All other DRAM settings

such as AL and CL may be changed at any time.

10.2.3.1

Write Timing

Figure 10-2 illustrates write timing with the tester set to WL=3, 4, and 5. There is a

constant offset of three cycles from TDRV to TDQ and one cycle from TDQ to DRAM DQ.

The DRAM mode registers must, of course, be set to the appropriate timing to

recognize the read. For BL=8 the TDRV pulse will be 4 clocks wide rather than 2.

10.2.3.2

Extended Write Timing

The TDRV pulse may be extended indefinitely in cases where it is necessary to apply

constant data to the DRAM pins. As long as TDRV remains asserted the AMB will

continuously propagate data from the tester TDQ inputs through to the DRAM DQ pins

(delayed by 1 cycle) as indicated below.

Figure 10-1. Transparent Mode Timing

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