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MC9S08DZ96F2CLL bảng dữ liệu(PDF) 155 Page - Freescale Semiconductor, Inc

tên linh kiện MC9S08DZ96F2CLL
Giải thích chi tiết về linh kiện  Microcontrollers
PDF  458 Pages
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nhà sản xuất  FREESCALE [Freescale Semiconductor, Inc]
Trang chủ  http://www.freescale.com
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MC9S08DZ96F2CLL bảng dữ liệu(HTML) 155 Page - Freescale Semiconductor, Inc

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Chapter 7 Central Processor Unit (S08CPUV5)
MC9S08DZ128 Series Data Sheet, Rev. 1
Freescale Semiconductor
155
BPL rel
Branch if Plus (if N = 0)
REL
2A rr
3
ppp
–11–
––––
BRA rel
Branch Always (if I = 1)
REL
20 rr
3
ppp
–11–
––––
BRCLR n,opr8a,rel
Branch if Bit n in Memory Clear (if (Mn) = 0)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
–11–
–––
↕
BRN rel
Branch Never (if I = 0)
REL
21 rr
3
ppp
–11–
––––
BRSET n,opr8a,rel
Branch if Bit n in Memory Set (if (Mn) = 1)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
rpppp
–11–
–––
↕
BSET n,opr8a
Set Bit n in Memory (Mn
← 1)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
rfwpp
–11–
––––
BSR rel
Branch to Subroutine
PC
← (PC) + $0002
push (PCL); SP
← (SP) – $0001
push (PCH); SP
← (SP) – $0001
PC
← (PC) + rel
REL
AD rr
5
ssppp
–11–
––––
CALL page, opr16a
Call Subroutine
EXT
AC pg hhll
8
ppsssppp
–11–
––––
CBEQ opr8a,rel
CBEQA #opr8i,rel
CBEQX #opr8i,rel
CBEQ oprx8,X+,rel
CBEQ ,X+,rel
CBEQ oprx8,SP,rel
Compare and...
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (X) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
Branch if (A) = (M)
DIR
IMM
IMM
IX1+
IX+
SP1
31
41
51
61
71
9E 61
dd rr
ii rr
ii rr
ff rr
rr
ff rr
5
4
4
5
5
6
rpppp
pppp
pppp
rpppp
rfppp
prpppp
–11–
––––
CLC
Clear Carry Bit (C
← 0)
INH
98
1
p
–11–
–––0
CLI
Clear Interrupt Mask Bit (I
← 0)
INH
9A
1
p
–11–
0–––
CLR opr8a
CLRA
CLRX
CLRH
CLR oprx8,X
CLR ,X
CLR oprx8,SP
Clear
M
← $00
A
← $00
X
← $00
H
← $00
M
← $00
M
← $00
M
← $00
DIR
INH
INH
INH
IX1
IX
SP1
3F
4F
5F
8C
6F
7F
9E 6F
dd
ff
ff
5
1
1
1
5
4
6
rfwpp
p
p
p
rfwpp
rfwp
prfwpp
011–
–01–
Table 7-2. Instruction Set Summary (Sheet 3 of 9)
Source
Form
Operation
Object Code
Cyc-by-Cyc
Details
Affect
on CCR
V 1 1 H
I N Z C



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