AT90SCR100 datasheet(258/433 Pages) ATMEL

258 / 433 page

258

TPR0327AY–SMS–30Jan09

AT90SCR100

BAUD

Baud rate (in bits per second, bps)

OSC

System Oscillator clock frequency: clkIO

UBRR0

Contents of the UBRR0H and UBRR0L Registers, (0-4095)

19.4

SPI Data Modes and Timing

There are four combinations of XCK0 (SCK) phase and polarity with respect to serial data, which

are determined by control bits UCPHA0 and UCPOL0. The data transfer timing diagrams are

shown in Figure 19-1. Data bits are shifted out and latched in on opposite edges of the XCK0

signal, ensuring sufficient time for data signals to stabilize. The UCPOL0 and UCPHA0 function-

ality is summarized in Table 19-2. Note that changing the setting of any of these bits will corrupt

all ongoing communication for both the Receiver and Transmitter.

Table 19-1.

Equations for Calculating Baud Rate Register Setting

Operating Mode

Equation for Calculating Baud

Rate

(1)

The baud rate is defined to be the transfer rate in bit per second (bps)

Equation for Calculating UBRR0

Value

Synchronous Master

mode

BAUD

OSC

2 UBRRn 1

()

---------------------------------------

UBRRn

OS C

2BAUD

--------------------

–

Table 19-2.

UCPOL0 and UCPHA0 Functionality-

UCPOL0

UCPHA0

SPI Mode

Leading Edge

Trailing Edge

Sample (Rising)

Setup (Falling)

Setup (Rising)

Sample (Falling)

Setup (Rising)

Setup (Falling)

Sample (Rising)

AT90SCR100 bảng dữ liệu(PDF) 258 Page - ATMEL Corporation

AT90SCR100 bảng dữ liệu(HTML) 258 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL