AT90SCR100 datasheet(192/433 Pages) ATMEL

192 / 433 page

192

TPR0327AY–SMS–30Jan09

AT90SCR100

Depending upon CREPSET bit is SCSR register, the receiver can indicate parity error up to

4times (3 repetitions) or up to 5times (4 repetitions) after which it will raise the parity error bit

SCPE bit in the SCISR register. If parity interrupt is enabled, the SCPI bit in SCIIR register will

be set too.

Alternately, the transmitter will detect ICC character repetition request. After 3 or 4 unsuccessful

repetitions (depending on CREPSEL bit in SCSR register), the transmitter will raise the parity

error bit SCPE bit in the SCISR register. If parity interrupt is enabled, the SCPI bit in SCIIR reg-

ister will be set too.

• Bit 0 – CONV: ISO Convention

Clear this bit to use the direct convention: b0 bit (LSB) is sent first, the parity bit is added after b7

bit and a low level on the Card I/O pin represents a’0’.

Set this bit to use the inverse convention: b7 bit (LSB) is sent first, the parity bit is added after b0

bit and a low level on the Card I/O pin represents a’1’.

15.7.2

SCCON - Smart Card Contacts Register

• Bit 7 – CLK: Card Clock Selection

Clear this bit to use the SCCON.CARDCLK bit to drive Card CLK pin.

Set this bit to use clkSCI signal to drive the Card CLK pin

• Bit 6 – Reserved Bit

This bit is reserved for future use.

• Bit 5 – CARDC8: Card C8

Clear this bit to drive a low level on the Card C8 pin (CC8 pin).

Set this bit to set a high level on the Card C8 pin (CC8 pin).

The CC8 pin can be used as a pseudo bi-directional I/O when this bit is set.

VCARDOK=1 (SCISR.4 bit) condition must be true to change the state of CC8 pin.

• Bit 4 – CARDC4: Card C4

Clear this bit to drive a low level on the Card C4 pin (CC4 pin).

Set this bit to set a high level on the Card C4 pin (CC4 pin).

Character repetition mode is specified for T=0 protocol only and should not be

used in T=1 protocol (block oriented protocol)

Note

Bit

$0000FE

CLK

CARDC8

CARDC4

CARDIO CARDCLK CARDRST CARDVCC

SCCON

Read/write

R/W

Initial value

0x00

Internal synchronization avoids glitches on the CLK pin when switching this bit.

Note

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