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AT90SCR100 bảng dữ liệu(PDF) 168 Page - ATMEL Corporation |
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AT90SCR100 bảng dữ liệu(HTML) 168 Page - ATMEL Corporation |
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168 / 433 page ![]() 168 TPR0327AY–SMS–30Jan09 AT90SCR100 • Bit 7 - Res : Reserved Bit This bit is a reserved bit in the AT90SCR100 and is always read as zero. • Bit 6 - IERR : Isochronous Error Bit This bit is a status bit. It is set (one) by hardware when the CRC of a packet received in an Isochronous transfer is incorrect or corrupted. If the CRC is correct the bit is cleared (zero) by hardware. This bit is not a source for the Endpoint interrupt. • Bit 5 - FSTALL : Force Stall Bit This bit is a control bit. It is set (one) and cleared (zero) by software. If it is set (one) the corresponding endpoint is stalled and the host immediately receives a STALL as response to the IN or OUT tokens sent to this endpoint (see procedure on next page). If it is cleared (zero) the corresponding endpoint is not stalled. This bit is not a source for the Endpoint interrupt. • Bit 4 - TXPB : Tx Packet Busy Bit This bit is a control bit. It is set (one) by software and cleared (zero) by hardware. If it is cleared (zero), the DPRAM bank corresponding to the endpoint is empty. It can then be filled with data to be sent. If it is set (one), the data present in the DPRAM bank is sent. This bit is not a source for the Endpoint interrupt. • Bit 3 - STSENT : Stall Sent Bit This bit is a status bit. It is set (one) by hardware and cleared (zero) by software. If it is set (one), a STALL has been sent from the corresponding endpoint to the host through the USB bus. This bit is a source for the Endpoint interrupt and must be cleared to acknowledge the interruption. • Bit 2 - RXSETUP : Rx Setup Bit This bit is a status bit. It is set (one) by hardware and cleared (zero) by software. If it is set (one) and if the corresponding endpoint operates with Control mode transfers, a valid Setup packet has been received from the host through the USB bus. This bit is a source for the Endpoint interrupt and must be cleared to acknowledge the interruption. |
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