AT90SCR100 datasheet(155/433 Pages) ATMEL

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TPR0327AY–SMS–30Jan09

AT90SCR100

13.4.1

GTCCR – General Timer/Counter Control Register

• Bit 7 – TSM : Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSRASY and PSRSYNC bits is kept, hence keeping the correspond-

ing prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are

halted and can be configured to the same value without the risk of one of them advancing during

configuration. When the TSM bit is written to zero, the PSRASY and PSRSYNC bits are cleared

by hardware, and the Timer/Counters start counting simultaneously.

• Bit 1 – PSRASY : Prescaler Reset Timer/Counter2

When this bit is one, the Timer/Counter2 prescaler will be reset. This bit is normally cleared

immediately by hardware. If the bit is written when Timer/Counter2 is operating in asynchronous

mode, the bit will remain one until the prescaler has been reset. The bit will not be cleared by

hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Syn-

chronization Mode” on page 136 for a description of the Timer/Counter Synchronization mode.

• Bit 0 – PSRSYNC : Prescaler Reset Timer/Counter0, Timer/Counter1

When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor-

mally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1

and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both

timers.

Bit

0x23 (0x43)

TSM

PSRASY PSRSYNC

GTCCR

Read/write

R/W

Initial value

0x00

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