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AT90SCR100 bảng dữ liệu(PDF) 114 Page - ATMEL Corporation

tên linh kiện AT90SCR100
Giải thích chi tiết về linh kiện  8-bit Microcontroller for Smart Card Readers
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Trang chủ  http://www.atmel.com
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AT90SCR100 bảng dữ liệu(HTML) 114 Page - ATMEL Corporation

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TPR0327AY–SMS–30Jan09
AT90SCR100
13.2.6
Output Compare Units
The 16-bit comparator continuously compares TCNT1 with the Output Compare Register
(OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output
Compare Flag
(OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Com-
pare Flag generates an Output Compare interrupt. The OCF1x Flag is automatically cleared
when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writ-
ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the Waveform Generation mode
(WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals
are used by the Waveform Generator for handling the special cases that occur in some modes
of operation when maximum and minimum values are reached (See “Modes of Operation” on
page 117.)
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e.,
counter resolution). In addition to the counter resolution, the TOP value defines the period time
for waveforms generated by the Waveform Generator.
Figure 13-15 shows a block diagram of the Output Compare unit. The “x” indicates Output Com-
pare unit (A/B/C). The elements of the block diagram that are not directly a part of the Output
Compare unit are gray shaded.
Figure 13-15.
Output Compare Unit, Block Diagram
The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation
(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCR1x Com-
pare Register to either TOP or BOTTOM of the counting sequence. The synchronization
prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the out-
put glitch-free.
OCF1x (Int.Req.)
= (16-bit Comparator )
OCR1x
Buffer (16-bit Register)
OCR1xH
Buf. (8-bit)
OC1x
TEMP (8-bit)
DATA BUS (8-bit)
OCR1xL
Buf. (8-bit)
TCNT1 (16-bit Counter)
TCNT1H (8-bit)
TCNT1L
(8-bit)
COM1x1:0
WGM13:0
OCR1x (16-bit Register)
OCR1xH
(8-bit)
OCR1xL
(8-bit)
Waveform Generator
TOP
BOTTOM



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