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AT45DB641E bảng dữ liệu(PDF) 8 Page - Renesas Technology Corp

tên linh kiện AT45DB641E
Giải thích chi tiết về linh kiện  64-Mbit DataFlash (with Extra 2-Mbits), 1.7 V Minimum SPI Serial Flash Memory
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nhà sản xuất  RENESAS [Renesas Technology Corp]
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DS-AT45DB641E-027 Rev. O
Page 8
6/30/23
© 2023 Renesas Electronics
AT45DB641E Datasheet
Table 1. Pin Configurations
Symbol
Name and Function
Asserted
State
Type
CS
Chip Select
Asserting the CS pin selects the device. When the CS pin is deasserted, the device is deselected
and placed in standby mode (not Deep Power-Down mode), and the output pin (SO) is in a high-
impedance state. When the device is deselected, data are not accepted on the input pin (SI).
A high-to-low transition on the CS pin is required to start an operation and a low-to-high transition
is required to end an operation. When ending an internally self-timed operation such as a
program or erase cycle, the device does not enter the standby mode until the operation is
completed.
Low
Input
SCK
Serial Clock
This pin provides a clock to the device and is used to control the flow of data to, and from, the
device. Command, address, and input data present on the SI pin are latched on the rising edge of
SCK, while output data on the SO pin are clocked out on the falling edge of SCK.
—
Input
SI
Serial Input
The SI pin is used to shift data into the device. The SI pin is used for all data input including
command and address sequences. Data on the SI pin are latched on the rising edge of SCK.
Data present on the SI pin are ignored whenever the device is deselected (CS is deasserted).
—
Input
SO
Serial Output
The SO pin is used to shift data out from the device. Data on the SO pin are clocked out on the
falling edge of SCK. The SO pin is in a high-impedance state whenever the device is deselected
(CS is deasserted).
—Output
WP
Write Protect
When the WP pin is asserted, all sectors specified for protection by the Sector Protection
Register are protected against program and erase operations regardless of whether the Enable
Sector Protection command has been issued or not. The WP pin functions independently of the
software controlled protection method. After the WP pin goes low, the contents of the Sector
Protection Register cannot be modified.If a program or erase command is issued to the device
while the WP pin is asserted, the device simply ignores the command and perform no operation.
The device returns to the idle state once the CS pin has been deasserted. The Enable Sector
Protection command and the Sector Lockdown command, however, are recognized by the device
when the WP pin is asserted.The WP pin is internally pulled-high and can be left floating if
hardware controlled protection is not used. However, it is recommended that the WP pin also be
externally connected to VCC whenever possible.
Low
Input
RESET
Reset
A low state on the reset pin (RESET) terminates the operation in progress and reset the internal
state machine to an idle state. The device remains in the reset condition as long as a low level is
present on the RESET pin. Normal operation can resume once the RESET pin is brought back to
a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions on the
RESET pin during power-on sequences. If this pin and feature is not used, then it is
recommended that the RESET pin be driven high externally.
Low
Input
VCC
Device Power Supply
The VCC pin is used to supply the source voltage to the device. Operations at invalid VCC
voltages can produce spurious results and must not be attempted.
—
Power
GND
Ground
The ground reference for the power supply. GND must be connected to the system ground.
—Ground



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