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DS3105 bảng dữ liệu(PDF) 60 Page - Maxim Integrated Products |
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DS3105 bảng dữ liệu(HTML) 60 Page - Maxim Integrated Products |
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60 / 110 page ![]() Preliminary. Subject to Change Without Notice. DS3105 Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement. 60 of 110 Register Name: MCR1 Register Description: Master Configuration Register 1 Register Address: 32h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name RST -- FREN LOCKPIN -- T0STATE[2:0] Default 0 0 1 0 0 0 0 0 Bit 7: Device Reset (RST). When this bit is high the entire device is held in reset, and all register fields, except the RST bit itself, are reset to their default states. When RST is active, the register fields with pin-programmed defaults do not latch their values from the corresponding input pins. Instead these fields are reset to the default values that were latched from the pins when the RST pin was last active. See section 7.11. 0 = Normal operation 1 = Reset Bit 5: Frequency Range Detect Enable (FREN). When this bit is high the frequency of each input clock is measured and used to quickly declare the input inactive. 0 = Frequency Range Detect disabled 1 = Frequency Range Detect enabled Bit 4: T0 DPLL LOCK Pin Enable (LOCKPIN). When this bit is high the LOCK pin indicates when the T0 DPLL state machine is in the LOCK state (OPSTATE.T0STATE=100). 0 = LOCK pin is not driven 1 = LOCK pin is driven high when the T0 DPLL is in the Lock state Bits 2 to 0: T0 DPLL State Control (T0STATE[2:0]). This field allows the T0 DPLL state machine to be forced to a specified state. The state machine will remain in the forced state, and therefore cannot react to alarms and other events, as long as T0STATE is not equal to 000. See section 7.7.1. 000 = Automatic (normal state machine operation) 001 = Free-run 010 = Holdover 011 = {unused value} 100 = Locked 101 = Pre-locked 2 110 = Pre-locked 111 = Loss-of-lock |
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