DS3105 datasheet(11/110 Pages) MAXIM

11 / 110 page

Preliminary. Subject to Change Without Notice.

DS3105

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

11 of 110

6 PIN DESCRIPTIONS

Table 6-1. Input Clock Pin Descriptions

Pin Name

(1)

Type

(2)

Pin Description

REFCLK

Reference Clock.

Connect to a 12.800 MHz, high-accuracy, high-stability, low-noise local oscillator (XO or

TCXO). See section 7.3.

IC3

IPD

Input Clock 3

CMOS/TTL. Programmable frequency (default 8 kHz).

This input can be associated with the SYNC1 pin.

IC4

IPD

Input Clock 4

CMOS/TTL. Programmable frequency (default 8 kHz).

This input can be associated with the SYNC2 pin.

IC5POS,

IC5NEG

IDIFF

Input Clock 5

LVDS/LVPECL or CMOS/TTL. Programmable frequency (default 19.44 MHz).

LVDS/LVPECL: see Table 10-4, Figure 10-1 and Figure 10-2.

CMOS/TTL: Bias IC5NEG to 1.4V and connect the single-ended signal to IC5POS.

This input can be associated with the SYNC1 pin.

IC6POS,

IC6NEG

IDIFF

Input Clock 6

LVDS/LVPECL or CMOS/TTL. Programmable frequency (default 19.44 MHz).

LVDS/LVPECL: see Table 10-4, Figure 10-1 and Figure 10-2.

CMOS/TTL: Bias IC6NEG to 1.4V and connect the single-ended signal to IC6POS.

This input can be associated with the SYNC2 pin.

IC9

IPD

Input Clock 9

CMOS/TTL. Programmable frequency (default 19.44 MHz).

This input can be associated with the SYNC3 pin.

SYNC1

IPD

Frame Sync1 Input

. 2 kHz, 4 kHz or 8 kHz.

FSCR3:SOURCE != 11XX

This pin is the external frame sync input associated with any input pin using the

FSCR3:SOURCE field.

FSCR3:SOURCE = 11XX

This pin is the external frame sync signal associated with IC3 or IC5 depending on

which one is currently selected and the setting of FSCR1.SYNCSRC[1:0].

SYNC2

IPD

Frame Sync2 Input

. 2 kHz, 4 kHz or 8 kHz.

FSCR3:SOURCE != 11XX

This pin is not used for the external frame sync signal.

FSCR3:SOURCE = 11XX

This pin is the external frame sync signal associated with IC4 or IC6 depending on

which one is currently selected and the setting of FSCR1.SYNCSRC[1:0].

SYNC3 / O3F0

IPU

Frame Sync3 Input

. 2 kHz, 4 kHz or 8 kHz. / OC3 Frequency Select 0.

This pin is sampled when the

RST pin goes high and the value is used as O3F0 which together

with O3F2 and O3F1 sets the default frequency of the OC3 output clock pin. See Table 7-18.

After

RST goes high this pin becomes the SYNC3 input pin (2, 4 or 8 kHz) associated with IC9.

It is only used as SYNC3 when FSCR2.SOURCE = 11XX.

Table 6-2. Output Clock Pin Descriptions

Pin Name

(1)

Type

(2)

Pin Description

OC3

Output Clock 3

CMOS/TTL. Programmable frequency. Default frequency selected by O3F[2:0] pins when the

RST pin goes high, 19.44 MHz if O3F[2:0] pins left open). See Table 7-18.

OC6POS,

OC6NEG

ODIFF

Output Clock 6

LVDS/LVPECL. Programmable frequency. Default frequency selected by O6F[2:0] pins when

the

RST pin goes high, 38.88 MHz if O6F[2:0] pins left open). The output mode is selected by

MCR8.OC6SF[1:0]. See Table 10-5, Table 10-6 , Figure 10-1 and Figure 10-3.

FSYNC

8 kHz FSYNC.

CMOS/TTL. 8 kHz frame sync or clock. (default 50% duty cycle clock, non-inverted) The pulse

polarity and width are selectable using FSCR1.8KINV and FSCR1.8KPUL.

MFSYNC

2 kHz MFSYNC.

CMOS/TTL. 2 kHz frame sync or clock. (default 50% duty cycle clock, non-inverted) The pulse

polarity and width are selectable using FSCR1.2KINV and FSCR1.2KPUL.

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