DS3105 datasheet(41/110 Pages) MAXIM

41 / 110 page

Preliminary. Subject to Change Without Notice.

DS3105

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

41 of 110

7.10 Microprocessor Interface

The device presents an SPI interface on the

CS, SCLK, SDI and SDO pins. SPI is a widely-used master/slave bus

protocol that allows a master device and one or more slave devices to communicate over a serial bus. The DS3105

is always a slave device. Masters are typically microprocessors, ASICs or FPGAs. Data transfers are always

initiated by the master device, which also generates the SCLK signal. The DS3105 receives serial data on the SDI

pin and transmits serial data on the SDO pin. SDO is high-impedance except when the DS3105 is transmitting data

to the bus master.

Bit Order.

When both bit 3 and bit 4 are low at device address 3FFFh, the register address and all data bytes are

transmitted MSB first on both SDI and SDO. When either bit 3 or bit 4 is set to 1 at device address 3FFFh, the

Motorola SPI convention is MSB first.

Clock Polarity and Phase.

SCLK is normally low and pulses high during bus transactions. The CPHA pin sets the

phase (active edge) of SCLK. When CPHA = 0, data is latched in on SDI on the leading edge of the SCLK pulse

and updated on SDO on the trailing edge. When CPHA = 1, data is latched in on SDI on the trailing edge of the

SCLK pulse and updated on SDO on the following leading edge. SCLK does not have to toggle between accesses,

i.e., when

CS is high. See Figure 7-4.

Device Selection.

Each SPI device has its own chip-select line. To select the DS3105, pull its

CS pin low.

Control Word.

After

CS is pulled low, the bus master transmits the control word during the first sixteen SCLK

cycles. In MSB-first mode the control word has the form:

W A13 A12 A11 A10 A9 A8 A7

A6 A5 A4 A3 A2 A1 A0 BURST

where A[13:0] is the register address, R/

W is the data direction bit (1=read, 0=write), and BURST is the burst bit

(1=burst access, 0=single-byte access). In LSB-first mode the order of the fourteen address bits is reversed. In the

discussion that follows, a control word with R/

W = 1 is a read control word, while a control word with R/W = 0 is a

write control word.

Single-Byte Writes.

See Figure 7-5. After CS goes low, the bus master transmits a write control word with

BURST=0 followed by the data byte to be written. The bus master then terminates the transaction by pulling

high.

Single-Byte Reads.

See Figure 7-5. After CS goes low, the bus master transmits a read control word with

BURST=0. The DS3105 then responds with the requested data byte. The bus master then terminates the

transaction by pulling

CS high.

Burst Writes.

See Figure 7-5. After CS goes low, the bus master transmits a write control word with BURST=1

followed by the first data byte to be written. The DS3105 receives the first data byte on SDI, writes it to the

specified register, increments its internal address register, and prepares to receive the next data byte. If the master

continues to transmit, the DS3105 continues to write the data received and increment its address counter. After the

address counter reaches 3FFFh it rolls over to address 0000h and continues to increment.

Burst Reads.

See Figure 7-5. After CS goes low, the bus master transmits a read control word with BURST=1.

The DS3105 then responds with the requested data byte on SDO, increments its address counter, and prefetches

the next data byte. If the bus master continues to demand data, the DS3105 continues to provide the data on SDO,

increment its address counter, and pre-fetch the following byte. After the address counter reaches 3FFFh it rolls

over to address 0000h and continues to increment.

Early Termination of Bus Transactions.

The bus master can terminate SPI bus transactions at any time by

pulling

CS high. In response to early terminations, the DS3105 resets its SPI interface logic and waits for the start

of the next transaction. If a write transaction is terminated prior to the SCLK edge that latches the LSB of a data

byte, the data byte is not written.

Design Option: Wiring SDI and SDO Together.

Because communication between the bus master and the

DS3105 is half-duplex, the SDI and SDO pins can be wired together externally to reduce wire count. To support

this option, the bus master must not drive the SDI/SDO line when the DS3105 is transmitting.

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