DS3105 datasheet(44/110 Pages) MAXIM

44 / 110 page

Preliminary. Subject to Change Without Notice.

DS3105

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

44 of 110

The DS3105 has an overall address range from 000h to 1FFh. Table 8-1 in section 8.4 shows the register map. In

each register, bit 7 is the MSB and bit 0 is the LSB. Register addresses not listed and bits marked “--“ are reserved

and must be written with 0. Writing other values to these registers may put the device in a factory test mode

resulting in undefined operation. Bits labeled “0” or “1” must be written with that value for proper operation. Register

fields with underlined names are read-only fields; writes to these fields have no effect. All other fields are read-

write. Register fields are described in detail in the register descriptions that follow Table 8-1.

8.1

Status Bits

The device has two types of status bits. Real-time status bits are read-only and indicate the state of a signal at the

time it is read. Latched status bits are set when a signal changes state (low-to-high, high-to-low, or both, depending

on the bit) and cleared when written with a logic 1 value. Writing a 0 has no effect. When set, some latched status

bits can cause an interrupt request on the INTREQ pin if enabled to do so by corresponding interrupt enable bits.

ISR#.LOCK# are special-case latched status bits because they cannot create an interrupt request on the INTREQ

pin and a “write 0” is needed to clear them.

8.2

Configuration Fields

Configuration fields are read-write. During reset, each configuration field reverts to the default value shown in the

8.3

Multi-Register Fields

Multi-register fields—such as FREQ[18:0] in registers FREQ1, FREQ2 and FREQ3—must be handled carefully to

ensure that the bytes of the field remain consistent. A write access to a multi-register field is accomplished by

writing all the registers of the field in any order, with no other accesses to the device in between. If the write

sequence is interrupted by another access, none of the bytes are written and the MSR4:MRAA latched status bit is

set to indicate the write was aborted. A read access from a multi-register field is accomplished by reading the

registers of the field in any order, with no other accesses to the device in between. When one register of a multi-

register field is read, the other register(s) in the field are frozen until after they are all read. If the read sequence is

interrupted by another access, the registers of the multi-byte field are unfrozen and the MSR4:MRAA bit is set to

indicate the read was aborted. For best results, interrupt servicing should be disabled in the microprocessor before

a multi-register access and then enabled again after the access is complete. The multi-register fields are:

Field

Registers

Addresses

Type

FREQ[18:0]

FREQ1, FREQ2, FREQ3

07, 0C, 0D

read-only

MCLKFREQ[15:0]

MCLK1, MCLK2

3C, 3D

read/write

HARDLIM[9:0]

DLIMIT1, DLIMIT2

41, 42

read/write

DIVN[15:0]

DIVN1, DIVN2

46, 47

read/write

OFFSET[15:0]

OFFSET1, OFFSET2

70, 71

read/write

PHASE[15:0]

PHASE1, PHASE2

77, 78

read-only

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