DS3105 datasheet(85/110 Pages) MAXIM

85 / 110 page

Preliminary. Subject to Change Without Notice.

DS3105

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

85 of 110

GPSR

GPIO Status Register

6Fh

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

GPIO4

GPIO3

GPIO2

GPIO1

Default

Bit 3: GPIO4 State (GPIO4).

This bit indicates the current state of the GPIO4 pin.

0 = low

1 = high

Bit 2: GPIO3 State (GPIO3).

This bit indicates the current state of the GPIO3 pin.

0 = low

1 = high

Bit 2: GPIO2 State (GPIO2).

This bit indicates the current state of the GPIO2 pin.

0 = low

1 = high

Bit 1: GPIO1 State (GPIO1).

This bit indicates the current state of the GPIO1 pin.

0 = low

1 = high

OFFSET1

Phase Offset Register 1

70h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

OFFSET[7:0]

Default

The OFFSET1 and OFFSET2 registers must be read consecutively and written consecutively. See section 8.3.

Bits 7 to 0: Phase Offset (OFFSET[7:0]).

The full 16-bit OFFSET[15:0] field spans this register and the OFFSET2

clocks and the selected input reference. The phase offset in picoseconds is equal to OFFSET[15:0] *

actual_internal_clock_period / 2

11. If the internal clock is at its nominal frequency of 77.76 MHz then the phase

offset equation simplifies to OFFSET[15:0] * 6.279 ps. If, however, the DPLL is locked to a reference whose

frequency is +1 ppm from ideal, for example, then the actual internal clock period is 1 ppm shorter and the phase

offset is 1 ppm smaller. When the OFFSET field is written, the phase of the output clocks is automatically ramped

to the new offset value to avoid loss of synchronization. To adjust the phase offset without changing the phase of

the output clocks, use the recalibration process enabled by FSCR3:RECAL. The OFFSET field is ignored when

phase build-out is enabled (PBOEN=1 in the MCR10 register) and when the DPLL is not locked. See section 7.7.8.

OFFSET2

Phase Offset Register 2

71h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

OFFSET[15:8]

Default

Bits 7 to 0: Phase Offset (OFFSET[15:8]).

See the OFFSET1 register description.

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