DS3105 datasheet(39/110 Pages) MAXIM

39 / 110 page

Preliminary. Subject to Change Without Notice.

DS3105

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

39 of 110

same timing card. The expected timing of the SYNCn signal with respect to the sampling clock can be adjusted

from 0.5 cycles early to 1 cycle late using the FSCR2:PHASEn[1:0] field.

7.9.2

Resampling

The SYNCn signal is then resampled by an internal clock derived from the T0 DPLL. The resampling resolution is a

function of the frequency of the selected reference and FSCR2:OCN. When OCN=0, the resampling resolution is

6.48 MHz, which gives the highest sampling margin and also aligns clocks at 6.48 MHz and multiples thereof.

When OCN=1, if the selected reference is 19.44 MHz then the resampling resolution is 19.44 MHz. If the selected

reference is 38.88 MHz then the resampling resolution is 38.88 MHz. The selected reference must be either 19.44

MHz or 38.88 MHz.

7.9.3

Enable

The SYNCn signal is only allowed to align output clocks if the T0 DPLL is locked and the SYNCn signal is enabled

and qualified.

When FSCR3:SOURCE[3:0] != 11XX, external frame sync on the SYNC1 pin can be enabled automatically or

manually. When MCR3:AEFSEN=1, external frame sync is enabled automatically when EFSEN=1 and the T0

DPLL is locked to the input clock specified by FSCR3:SOURCE[3:0]. When AEFSEN=0, external frame sync is

enabled manually when MCR3:EFSEN=1 and disabled when EFSEN=0. In manual mode when EFSEN=1,

FSCR3:SOURCE[3:0] is ignored and external frame sync is always enabled regardless of which input clock is the

selected reference.

When FSCR3:SOURCE[3:0] = 11XX, external frame sync from the SYNCn pins can be enabled when EFSEN=1

and the associated input clock becomes the selected reference. MCR3:AEFSEN can be used to automatically

disable EFSEN when the selected reference changes. See section 7.9.2.

7.9.4

Qualification

The SYNCn signal is qualified when it has consistent phase and correct frequency. Specifically, it is qualified when

its significant edge has been found at exact 2 kHz boundaries (when resampled as described above) for 64 cycles

in a row. It is disqualified when one significant edge is not found at the 2 kHz boundary. If there is no SYNCn signal

or a bad SYNCn signal, and external frame sync is enabled, the SYNCn signal will never get qualified and the 2

kHz output will simply free-run at its current 2 kHz alignment.

7.9.5

Output Clock Alignment

When the T0 DPLL is locked, external frame sync is enabled and the SYNCn signal is qualified, the SYNCn signal

can be used to falling-edge align the T0 DPLL derived output clocks. Output clocks FSYNC and MFSYNC share a

2-kHz alignment generator, while the rest of the T0 DPLL derived output clocks share a second 2-kHz alignment

generator. When external frame sync is not enabled or the SYNCn signal is not qualified, these 2-Hz alignment

generators free-run with their existing 2-kHz alignments. When external frame sync is enabled and the SYNCn

signal is qualified, the FSYNC/MFSYNC 2-kHz alignment generator is always synchronized by SYNCn, and

therefore FSYNC and MFSYNC are always falling-edge aligned with SYNCn. When FSCR2:INDEP=0, the T0

DPLL 2-kHz alignment generator is also synchronized with the FSYNC/MFSYNC 2-kHz alignment generator to

falling-edge align all T0-derived output clocks with SYNCn. When INDEP=1, the T0 DPLL 2-kHz alignment

generator is not synchronized with the FSYNC/MFSYNC 2-kHz alignment generator and continues to free-run with

its existing 2-kHz alignment. This avoids any disturbance on the T0 DPLL derived output clocks when SYNCn has

a change of phase position.

7.9.6

Frame Sync Monitor

The frame sync monitor signal OPSTATE:FSMON operates in two modes, depending on the setting of the enable

bit (MCR3:EFSEN).

When EFSEN = 1 (external frame sync enabled) the OPSTATE:FSMON bit is set when SYNCn is not qualified and

cleared when SYNCn is qualified. If SYNCn is disqualified then both 2 kHz alignment generators are immediately

disconnected from SYNCn to avoid phase movement on the T0-derived outputs clocks. When OPSTATE:FSMON

is set, the latched status bit MSR3:FSMON is also set, which can cause an interrupt if enabled in the IER3 register.

If SYNCn immediately stabilizes at a new phase and proper frequency, then it is requalified after 64 2 kHz cycles

(nominally 32 ms). Unless system software intervenes, after SYNCn is requalified the 2 kHz alignment generators

will synchronize with SYNCn’s new phase alignment, causing a sudden phase movement on the output clocks.

System software can avoid this sudden phase movement on the output clocks by responding to the FSMON

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