DS3105 datasheet(81/110 Pages) MAXIM

81 / 110 page

Preliminary. Subject to Change Without Notice.

DS3105

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

81 of 110

T4CR2

T4 Configuration Register 2

6Ah

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

PD2G8K[2:0]

DAMP[2:0]

Default

Bits 6 to 4: Phase Detector 2 Gain 8 kHz (PD2GA8K[2:0]).

This field specifies the gain of the T4 phase detector

2 with an input clock of 8 kHz or less. This value is only used if automatic gain selection is enabled by setting

PD2EN=1 in the T4CR3 register. See section 7.7.5.

Bits 2 to 0: Damping Factor (DAMP[2:0]).

This field configures the damping factor of the T4 DPLL. Damping

factor is a function of both DAMP[2:0] and the T4 DPLL bandwidth (T4BW register). The default value corresponds

to a damping factor of 5. See section 7.7.4.

18 Hz

35 Hz

≥ 70 Hz

001 =

1.2

010 =

2.5

011 =

100 =

101 =

000, 110 and 111 = {unused values}

The gain peak for each damping factor is shown below:

Damping Factor

Gain Peak

1.2

0.4 dB

2.5

0.2 dB

0.1 dB

0.06 dB

0.03 dB

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