DS3105 datasheet(22/110 Pages) MAXIM

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Preliminary. Subject to Change Without Notice.

DS3105

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

22 of 110

7.7

DPLL Architecture and Configuration

Both the T0 DPLL and T4 DPLL are digital PLLs. The T0 DPLL has separate analog PLLs (APLLs) as output

stages as well as some outputs that are not cleaned up by an APLL. This architecture combines the benefits of

both PLL types. See Figure 7-1.

Figure 7-1. DPLL Block Diagram

T0 DPLL

T4 DPLL

Locking

Frequency

PFD and

Loop Filter

Foward

DFS

Feedback

DFS

DIG12

DFS

T0 selected

reference

OC3, OC6

Foward

DFS

Feedback

DFS

PFD and

Loop Filter

Locking

Frequency

T4 selected

reference

T0CR1:T0FREQ[2:0]

OCRm:OFREQn[3:0]

OCR5:AOFn

T0CR1:T4MT0

T4CR1:T4FREQ[3:0]

T0CR1:T0FT4[2:0]

APLL

Output

Dividers

Output

APLL

DFS

APLL

Output

Dividers

Output

APLL

DFS

DIG12

DFS

2K8K

DFS

MCR6:DIG2SS

MCR6:DIG2F[1:0]

MCR6:DIG2AF

MCR6:DIG1SS

MCR6:DIG1F[1:0]

OUTPUT DFS

FSYNC

DFS

SYNC2K

FSCR2:INDEP

DIG2

DIG1

2K8K

ICRn:FREQ[3:0]

APLL

Output

Dividers

Output

APLL2

DFS

FSYNC,

MFSYNC

OCR4:FSEN, MFSEN

FSCR1:8KINV, 2KINV

FSCR1:8KPOL, 2KPOL

PLL Bypass

Digital PLLs have two key benefits: (1) stable, repeatable performance that is insensitive to process variations,

temperature and voltage, and (2) flexible behavior that is easily programmed via configuration registers. DPLLs use

digital frequency synthesis (DFS) to generate various clocks. In DFS a high-speed master clock (204.8 MHz) is

multiplied up from the 12.800 MHz local oscillator clock applied to the REFCLK pin. This master clock is then

digitally divided down to the desired output frequency. The DFS output clock has jitter of about 1 nsec pk-pk.

The analog PLLs filter the jitter from the DPLLs, reducing the 1 ns pk-pk jitter to less than 0.5 ns pk-pk and 60 ps

RMS, typical, measured broadband (10 Hz to 1 GHz).

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