DS3105 datasheet(38/110 Pages) MAXIM

38 / 110 page

Preliminary. Subject to Change Without Notice.

DS3105

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

38 of 110

7.8.2.5

FSYNC and MFSYNC Configuration

The FSYNC output is enabled by setting FSEN=1 in the OCR4 register, while the MFSYNC output is enabled by

setting MFSEN=1 in OCR4. When disabled, these pins are driven low.

When 8KPUL=0 in FSCR1, FSYNC is configured as an 8 kHz clock with 50% duty cycle. When 8KPUL=1, FSYNC

is an 8 kHz frame sync that pulses low once every 125

μs with pulse width equal to one cycle of output clock OC3.

When 8KINV=1 in FSCR1, the clock or pulse polarity of FSYNC is inverted.

When 2KPUL=0 in FSCR1, MFSYNC is configured as an 2 kHz clock with 50% duty cycle. When 2KPUL=1,

MFSYNC is a 2 kHz frame sync that pulses low once every 500

μs with pulse width equal to one cycle of output

clock OC3. When 2KINV=1 in FSCR1, the clock or pulse polarity of MFSYNC is inverted.

If either 8KPUL=1 or 2KPUL=1, then output clock OC3 must be generated from the T0 DPLL and must be

configured for a frequency of 1.544 MHz or higher or the FSYNC/MFSYNC pulses may not be generated correctly.

Figure 7-3 shows how the 8KPUL and 8KINV control bits affect the FSYNC output. The 2KPUL and 2KINV bits

have an identical effect on MFSYNC.

Figure 7-3. FSYNC 8 kHz Options

OC3 output clock

FSYNC, 8KPUL=0, 8KINV=0

FSYNC, 8KPUL=0, 8KINV=1

FSYNC, 8KPUL=1, 8KINV=0

FSYNC, 8KPUL=1, 8KINV=1

7.8.2.6

Custom Output Frequencies

In addition to the many standard frequencies available in the device, any of the seven output DFS blocks can be

configured to generate a custom frequency. Possible custom frequencies include any multiple of 2 kHz up to 77.76

MHz and any multiple of 8 kHz up to 311.04 MHz. (An APLL must be used to achieve frequencies above 77.76

MHz.) Any of the programmable output clocks can be configured to output the custom frequency or submultiples

thereof. Contact the factory at telecom.support@dalsemi.com for help with custom frequencies.

7.9

Frame and Multiframe Alignment

In addition to receiving and locking to clocks such as 19.44 MHz from system timing cards, the DS3105 can also

receive and align its outputs to 2 kHz multiframe sync or 8 kHz frame sync signals from system timing cards. In this

mode of operation, both a higher-speed clock (such as 6.48 MHz or 19.44 MHz) and a frame (or multiframe) sync

signal from each timing card are passed to the line cards. The higher-speed clock from each timing card is

connected to a regular input clock pin on the DS3105, such as IC3 or IC4, while the frame sync signal is connected

to a SYNCn input pin on the DS3105, such as SYNC1 or SYNC2. The DS3105 locks to the higher-speed clock

from one of the timing cards and samples the frame sync signal on the associated SYNCn pin. The DS3105 then

uses the SYNCn signal to falling-edge align some or all of the output clocks. Only the falling edge of the SYNCn

signal has significance. A 4 kHz or 8 kHz clock can also be used on the SYNCn pins without any changes to the

be disabled (PBOEN=0 in MCR10) when using SYNCn signals.

When FSCR3.SOURCE!=11XX, the frame sync signal can only come from the SYNC1 pin. When

FSCR3.SOURCE=11XX, the frame sync signal comes from one of SYNC1, SYNC2 or SYNC3. See section 7.9.7.

7.9.1

Sampling

By default the SYNCn signal is first sampled on the rising edge of the selected reference. This gives the most

margin, given that the SYNCn signal is falling-edge aligned with the selected reference since both come from the

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