DS3105 datasheet(51/110 Pages) MAXIM

51 / 110 page

Preliminary. Subject to Change Without Notice.

DS3105

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

51 of 110

MSR3

Master Status Register 3

08h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

FSMON

T4LOCK

Default

Bit 7: Frame Sync Input Monitor Alarm (FSMON).

This latched status bit is set to 1 when OPSTATE:FSMON

transitions from 0 to 1. FSMON is cleared when written with a 1. When FSMON is set it can cause an interrupt

request on the INTREQ pin if the FSMON interrupt enable bit is set in the IER3 register. See section 7.9.

Bit 6: T4 DPLL Lock Status Change (T4LOCK).

This latched status bit is set to 1 when the lock status of the T4

DPLL (OPSTATE:T4LOCK) changes (becomes locked when previously unlocked or becomes unlocked when

previously locked). T4LOCK is cleared when written with a 1 and not set again until the T4 lock status changes

again. When T4LOCK is set it can cause an interrupt request on the INTREQ pin if the T4LOCK interrupt enable bit

is set in the IER3 register. See section 7.7.6.

OPSTATE

Operating State Register

09h

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Name

FSMON

T4LOCK

T0SOFT

T4SOFT

T0STATE[2:0]

Default

Bit 7: Frame Sync Input Monitor Alarm (FSMON).

This real-time status bit indicates the current status of the

frame sync input monitor. See section 7.9.6.

0 = no alarm

1 = alarm

Bit 6: T4 DPLL Lock Status (T4LOCK).

This real-time status bit indicates the current phase lock status of the T4

DPLL. See sections 7.5.3 and 7.7.6.

0 = not locked to selected reference

1 = locked to selected reference

Bit 5: T0 DPLL Frequency Soft Alarm (T0SOFT).

This real-time status bit indicates whether or not the T0 DPLL is

tracking its reference within the soft alarm limits specified in the SOFT[6:0] field of the DLIMIT3 register. See

section 7.7.6.

0 = No alarm; frequency is within the soft alarm limits

1 = Soft alarm; frequency is outside the soft alarm limits

Bit 4: T4 DPLL Frequency Soft Alarm (T4SOFT).

This real-time status bit indicates whether or not the T4 DPLL is

tracking its reference within the soft alarm limits specified in the SOFT[6:0] field of the DLIMIT3 register. See

section 7.7.6.

0 = No alarm; frequency is within the soft alarm limits

1 = Soft alarm; frequency is outside the soft alarm limits

Bits 2 to 0: T0 DPLL Operating State (T0STATE[2:0]).

This real-time status field indicates the current state of the

T0 DPLL state machine. Values not listed below correspond to invalid (unused) states. See section 7.7.1.

001 = Free-run

010 = Holdover

100 = Locked

101 = Pre-locked 2

110 = Pre-locked

111 = Loss-of-lock

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