DS3105 datasheet(25/110 Pages) MAXIM

25 / 110 page

Preliminary. Subject to Change Without Notice.

DS3105

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

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7.7.1.4

Loss-of-Lock State

When the loss-of-lock detectors (see section 7.7.6) indicate loss of phase lock, the state machine immediately

transitions from the locked state to the loss-of-lock state. In the loss-of-lock state the DPLL tries for 100 seconds

(default value of PHLKTO register) to regain phase lock. If phase lock is regained during that period for more than

2 seconds then the state machine transitions back to the locked state.

If, during the phase-lock time-out period specified by PHLKTO, the selected reference is so impaired that an

activity alarm is raised (corresponding ACT bit set in the ISR registers), then the selected reference is invalidated

(ICn bit goes low in VALSR registers), and after being invalid for 2 seconds the state machine transitions to either

the pre-locked 2 state (if another valid input clock is available) or the holdover state (if no other input clock is valid).

If phase lock cannot be regained by the end of the phase-lock time-out period then a phase lock alarm is raised

(corresponding LOCK bit set in the ISR registers), the selected reference is invalidated (ICn bit goes low in VALSR

registers), and the state machine transitions to either the pre-locked 2 state (if another valid input clock is available)

or, after being invalid for 2 seconds, to the holdover state (if no other input clock is valid).

7.7.1.5

Prelocked 2 State

The pre-locked and pre-locked 2 states are similar. The pre-locked 2 state provides a 100-second period (default

value of PHLKTO register) for the DPLL to lock to the new selected reference. If phase lock (see section 7.7.6) is

achieved for more than 2 seconds during this period then the state machine transitions to locked mode.

If the DPLL fails to lock to the new selected reference within the phase-lock time-out period specified by PHLKTO

then a phase lock alarm is raised (corresponding LOCK bit set in the ISR registers), invalidating the input (ICn bit

goes low in VALSR registers). If another input clock is valid then the state machine re-enters the pre-locked 2 state

and tries to lock to the alternate input clock. If no other input clocks are valid for 2 seconds then the state machine

transitions to the holdover state.

In revertive mode (REVERT=1 in MCR3), if a higher-priority input clock becomes valid during the phase-lock time-

out period then the state machine re-enters the pre-locked 2 state and tries to lock to the higher-priority input.

If a phase-lock time-out period longer than 100 seconds is required for locking, then the PHLKTO register must be

configured accordingly.

7.7.1.6

Holdover State

The device reaches the holdover state when it declares its selected reference invalid for 2 seconds and has no

other valid input clocks available. During holdover the T0 DPLL is not phase locked to any input clock but instead

generates its output frequency from stored frequency information acquired while it was in the locked state. When at

least one input clock has been declared valid the state machine immediately transitions from holdover to the pre-

locked 2 state and tries to lock to the highest priority valid clock.

7.7.1.6.1

Automatic Holdover

For automatic holdover (FRUNHO=0 in MCR3), the device can be further configured for instantaneous mode or

averaged mode. In instantaneous mode (AVG=0 in HOCR3), the holdover frequency is set to the DPLL’s current

frequency 50 to 100 ms before entry into holdover (i.e. the value of the FREQ field in the FREQ1, FREQ2 and

FREQ3 registers when MCR11:T4T0=0). The FREQ field is the DPLL’s integral path and therefore is an average

frequency with a rate of change inversely proportional to the DPLL bandwidth. The DPLL’s proportional path is not

used in order to minimize the effect of recent phase disturbances on the holdover frequency.

In averaged mode (AVG=1 in HOCR3 and FRUNHO=1 in MCR3), the holdover frequency is set to an internally

averaged value. During locked operation the frequency indicated in the FREQ field is internally averaged over a

one-second period. The T0 DPLL indicates that it has acquired a valid holdover value by setting the HORDY status

bit in VALSR2 (real-time status) and MSR4 (latched status). If the T0 DPLL must enter holdover before the 1-

second average is available, an instantaneous value 50 to 100 ms old from the integral path is used instead.

7.7.1.6.2

Free-Run Holdover

For free-run holdover (FRUNHO=1 in MCR3), the output frequency accuracy is generated with the accuracy of the

external oscillator frequency. The actual frequency is the frequency of the external oscillator plus the value of the

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