DS3105 datasheet(2/110 Pages) MAXIM

2 / 110 page

Preliminary. Subject to Change Without Notice.

DS3105

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

2 of 110

TABLE OF CONTENTS

STANDARDS COMPLIANCE ............................................................................................................................... 6

APPLICATION EXAMPLE..................................................................................................................................... 7

BLOCK DIAGRAM ................................................................................................................................................ 7

DETAILED DESCRIPTION ................................................................................................................................... 8

DETAILED FEATURES......................................................................................................................................... 9

PIN DESCRIPTIONS .......................................................................................................................................... 11

FUNCTIONAL DESCRIPTION............................................................................................................................ 15

7.1

Overview.................................................................................................................................................... 15

7.2

Device Identification and Protection .......................................................................................................... 16

7.3

Local Oscillator and Master Clock Configuration ...................................................................................... 16

7.4

Input Clock Configuration .......................................................................................................................... 16

7.4.1

Signal Format Configuration......................................................................................................... 16

7.4.2

Frequency Configuration .............................................................................................................. 17

7.5

Input Clock Monitoring............................................................................................................................... 18

7.5.1

Frequency Monitoring................................................................................................................... 18

7.5.2

Activity Monitoring ........................................................................................................................ 18

7.5.3

Selected Reference Activity Monitoring........................................................................................ 19

7.6

Input Clock Priority, Selection and Switching ............................................................................................ 20

7.6.1

Priority Configuration .................................................................................................................... 20

7.6.2

Automatic Selection Algorithm ..................................................................................................... 20

7.6.3

Forced Selection........................................................................................................................... 21

7.6.4

Ultra-Fast Reference Switching.................................................................................................... 21

7.6.5

External Reference Switching Mode ............................................................................................ 21

7.6.6

Output Clock Phase Continuity During Reference Switching....................................................... 21

7.7

DPLL Architecture and Configuration........................................................................................................ 22

7.7.1

T0 DPLL State Machine ............................................................................................................... 23

7.7.2

T4 DPLL State Machine ............................................................................................................... 26

7.7.3

Bandwidth..................................................................................................................................... 26

7.7.4

Damping Factor ............................................................................................................................ 26

7.7.5

Phase Detectors ........................................................................................................................... 26

7.7.6

Loss of Phase Lock Detection...................................................................................................... 27

7.7.7

Phase Build-Out ........................................................................................................................... 28

7.7.8

Input to Output (Manual) Phase Adjustment ................................................................................ 28

7.7.9

Phase Recalibration ..................................................................................................................... 28

7.7.10 Frequency and Phase Measurement ........................................................................................... 29

7.7.11 Input Jitter Tolerance.................................................................................................................... 30

7.7.12 Jitter Transfer ............................................................................................................................... 30

7.7.13 Output Jitter and Wander ............................................................................................................. 30

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