DS3105 datasheet(30/110 Pages) MAXIM

30 / 110 page

Preliminary. Subject to Change Without Notice.

DS3105

Confidential. Document Issued Under Non-Disclosure Agreement. Confidential. Document Issued Under Non-Disclosure Agreement.

30 of 110

Table 7-5. T0 DPLL adaptation for the T4 DPLL Phase Measurement Mode

Locking Mode

for T4 Forced

Reference

Locking Mode

for T0 Selected

Reference

Locking Mode

for Copy of T0

Selected Ref

Frequency of the T4

Forced Ref for T4MT0

Phase Measurement

Frequency of the T0

Selected Ref for T4MT0

Phase Measurement

LOCK8K or

DIVN(8K)

DIRECT

LOCK8K

8 kHz

LOCK8K or

DIVN(8K)

LOCK8K

8 kHz

LOCK8K or

DIVN(8K)

DIVN (8K)

DIVN

8 kHz

LOCK8K or

DIVN(8K)

DIVN (not 8K)

DIRECT

8 kHz

DIVN (not 8K)

any

DIRECT

same as the T4 forced

ref input frequency

same as the T0 selected

ref input frequency

(1)

DIRECT

any

DIRECT

same as the T4 forced

ref input frequency

same as the T0 selected

ref input frequency

(1)

Notes:

In this case the T0 select reference must be the same frequency as the T4 selected reference.

If the T4 selected reference frequency is 8 kHz and the T0 selected reference is a different frequency, the two references can be compared

by configuring the T4 forced reference for 8 kHz and LOCK8K mode. This forces the copy of the T0 selected reference to be divided down

to 8 kHz using either LOCK8K or DIVN mode.

DIVN(8K) means that the FREQ field is set to 8 kHz, DIVN(not 8K) means the FREQ field is not set to 8 kHz.

7.7.11 Input Jitter Tolerance

The device is compliant with the jitter tolerance requirements of the standards listed in Table 1-1. When using the

±360° / ±180° PFD, jitter can be tolerated up to the point of eye closure. Either LOCK8K mode (see section 7.4.2.2)

or the multi-cycle phase detector (see section 7.7.5) should be used for high jitter tolerance.

7.7.12 Jitter Transfer

The transfer of jitter from the selected reference to the output clocks has a programmable transfer function that is

determined by the DPLL bandwidth. (See section 7.7.3.) In the T0 DPLL, the 3-dB corner frequency of the jitter

transfer function can be set to any of 13 positions from 0.1 Hz to 400 Hz. In the T4 DPLL the 3-dB corner frequency

of the jitter transfer function can be set to various values from 18 Hz to 70 Hz.

7.7.13 Output Jitter and Wander

Several factors contribute to jitter and wander on the output clocks, including:

•

Jitter and wander amplitude on the selected reference (while in the locked state)

•

The jitter transfer characteristic of the device (while in the locked state)

•

The jitter and wander on the local oscillator clock signal (especially wander while in the

holdover state)

The DPLL in the device has programmable bandwidth (see section 7.7.3). With respect to jitter, the DPLL behaves

as a low-pass filter with a programmable pole. The bandwidth of the DPLL is low enough to strongly attenuate most

jitter.

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