CLRC63201TSLASH0FE datasheet(50/163 Pages) PHILIPS

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Philips Semiconductors

Product Specification Rev. 3.0; May 2003

Multiple Protocol Contactless Reader IC

CL RC632

Confidential

5.2.4.8

ClockQControl Register

controls clock generation for the 90° phase shifted Q-channel clock.

Name: ClockQControl

Address: 0x1F

Reset value: 000XXXXX, 0xXX

ClkQ180Deg

ClkQCalib

ClkQDelay

Access

Rights

r/w

Description of the bits

Bit

Symbol

Function

ClkQ180Deg

If the Q-clock is phase shifted more than 180° compared to the I-clock, the bit

ClkQ180Deg is set to 1, otherwise it is 0.

ClkQCalib

If this bit is 0, the Q-clock is calibrated automatically after the Reset Phase and

after data reception from the card.

If this bit is set to 1, no calibration is performed automatically.

This value shall not be changed

4-0

ClkQDelay

This register shows the number of delay elements actually used to generate a

90°phase shift of the I-clock to obtain the Q-clock.

It can be written directly by the µ-Processor or by the automatic calibration cycle.

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