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TMPR4925 bảng dữ liệu(PDF) 235 Page - Toshiba Semiconductor

tên linh kiện TMPR4925
Giải thích chi tiết về linh kiện  64-Bit TX System RISC TX49 Family
PDF  590 Pages
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nhà sản xuất  TOSHIBA [Toshiba Semiconductor]
Trang chủ  http://www.semicon.toshiba.co.jp/eng
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TMPR4925 bảng dữ liệu(HTML) 235 Page - Toshiba Semiconductor

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Chapter 9 SDRAM Controller
9-7
9.3.2.3
Address Signal Mapping (16-bit Data Bus)
Table 9.3.3 shows the address signal mapping when using a 16-bit data bus. B0 is used in the
bank selection in memory with a two-bank configuration. [B1:B0] are used in the bank selection
in memory with a four-bank configuration. Bits with the description “L/H” output High when
performing auto-precharging, or output Low when not performing auto-precharging.
Table 9.3.3 Address Signal Mapping (16-bit Data Bus) (1/2)
Row Address Width = 11
Column Address Width = 8
Address Bit
ADDR [19:5]
19
(B0)
18
(B1)
17
16
SAD
DR10
(AP)
14
13
12
11
10
9
8
7
6
5
Column Address
20
21
21
20
L/H
21
20
8
7
6
5
4
3
2
1
Row Address
20
21
21
20
19
18
17
16
15
14
13
12
11
10
9
Row Address Width
= 11
Column Address Width
= 9
Address Bit
ADDR [19:5]
19
(B0)
18
(B1)
17
16
SAD
DR10
(AP)
14
13
12
11
10
9
8
7
6
5
Column Address
21
21
21
20
L/H
21
20
8
7
6
5
4
3
2
1
Row Address
21
21
21
20
19
18
17
16
15
14
13
12
11
10
9
Row Address Width
= 11
Column Address Width
= 10
Address Bit
ADDR [19:5]
19
(B0)
18
(B1)
17
16
SAD
DR10
(AP)
14
13
12
11
10
9
8
7
6
5
Column Address
22
21
21
20
L/H
21
20
8
7
6
5
4
3
2
1
Row Address
22
21
21
20
19
18
17
16
15
14
13
12
11
10
9
Row Address Width
= 12
Column Address Width
= 8
Address Bit
ADDR [19:5]
19
(B0)
18
(B1)
17
16
SAD
DR10
(AP)
14
13
12
11
10
9
8
7
6
5
Column Address
21
22
21
20
L/H
22
21
8
7
6
5
4
3
2
1
Row Address
21
22
21
20
19
18
17
16
15
14
13
12
11
10
9
Row Address Width
= 12
Column Address Width
= 9
Address Bit
ADDR [19:5]
19
(B0)
18
(B1)
17
16
SAD
DR10
(AP)
14
13
12
11
10
9
8
7
6
5
Column Address
22
23
21
20
L/H
22
21
8
7
6
5
4
3
2
1
Row Address
22
23
21
20
19
18
17
16
15
14
13
12
11
10
9
Row Address Width
= 12
Column Address Width
= 10
Address Bit
ADDR [19:5]
19
(B0)
18
(B1)
17
16
SAD
DR10
(AP)
14
13
12
11
10
9
8
7
6
5
Column Address
23
24
21
20
L/H
22
21
8
7
6
5
4
3
2
1
Row Address
23
24
21
20
19
18
17
16
15
14
13
12
11
10
9



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