TMPR4925 datasheet(10/590 Pages) TOSHIBA

10 / 590 page

Table of Contents

11.3.9

Reception Time Out .............................................................................................................................11-9

11.3.10 Software Reset .....................................................................................................................................11-9

11.3.11 Error Detection/Interrupt Signaling ...................................................................................................11-10

11.3.12 Multi-Controller System .................................................................................................................... 11-11

11.4

Registers .....................................................................................................................................................11-12

11.4.1

Line Control Register 0 (SILCR0) 0xF300 (Ch. 0),

Line Control Register 1 (SILCR1) 0xF400 (Ch. 1) ...........................................................................11-13

11.4.2

DMA/Interrupt Control Register 0 (SIDICR0) 0xF304 (Ch. 0),

DMA/Interrupt Control Register 1 (SIDICR1) 0xF404 (Ch. 1).........................................................11-14

11.4.3

DMA/Interrupt Status Register 0 (SIDISR0) 0xF308 (Ch. 0),

DMA/Interrupt Status Register 1 (SIDISR1) 0xF408 (Ch. 1)............................................................11-16

11.4.4

Status Change Interrupt Status Register 0 (SISCISR0) 0xF30C (Ch. 0),

Status Change Interrupt Status Register 1 (SISCISR1) 0xF40C (Ch. 1) ...........................................11-18

11.4.5

FIFO Control Register 0 (SIFCR0) 0xF310 (Ch. 0),

FIFO Control Register 1 (SIFCR1) 0xF410 (Ch. 1) ..........................................................................11-19

11.4.6

Flow Control Register 0 (SIFLCR0) 0xF314 (Ch. 0,

Flow Control Register 1 (SIFLCR1) 0xF414 (Ch. 1) ........................................................................11-20

11.4.7

Baud Rate Control Register 0 (SIBGR0) 0xF318 (Ch. 0),

Baud Rate Control Register 1 (SIBGR1) 0xF418 (Ch. 1)..................................................................11-21

11.4.8

Transmit FIFO Register 0 (SITFIFO0) 0xF31C (Ch. 0),

Transmit FIFO Register 1 (SITFIFO1) 0xF41C (Ch. 1) ....................................................................11-22

11.4.9

Receive FIFO Register 0 (SIRFIFO0) 0xF320 (Ch. 0),

Receive FIFO Register 1 (SIRFIFO1) 0xF420 (Ch. 1) ......................................................................11-23

12. Timer/Counter .......................................................................................................................................................12-1

12.1

Features.........................................................................................................................................................12-1

12.2

Block Diagram..............................................................................................................................................12-2

12.3

Detailed Explanation ....................................................................................................................................12-3

12.3.1

Overview..............................................................................................................................................12-3

12.3.2

Counter Clock ......................................................................................................................................12-3

12.3.3

Counter ................................................................................................................................................12-4

12.3.4

Interval Timer Mode ............................................................................................................................12-4

12.3.5

Pulse Generator Mode..........................................................................................................................12-6

12.3.6

Watchdog Timer Mode ........................................................................................................................12-7

12.4

Registers .......................................................................................................................................................12-9

12.4.1

Timer Control Register n (TMTCRn) TMTCR0 0xF000, TMTCR1 0xF100, TMTCR2 0xF200.....12-10

12.4.2

Timer Interrupt Status Register n (TMTISRn) TMTISR0 0xF004, TMTISR1 0xF104,

TMTISR2 0xF204..............................................................................................................................12-11

12.4.3

Compare Register An (TMCPRAn) TMCPRA0 0xF008, TMCPRA1 0xF108,

TMCPRA2 0xF208............................................................................................................................12-12

12.4.4

Compare Register Bn (TMCPRBn) TMCPRB0 0xF00C, TMCPRB1 0xF10C ................................12-13

12.4.5

Interval Timer Mode Register n (TMITMRn) TMITMR0 0xF010,

TMITMR1 0xF110, TMITMR2 0xF210 ...........................................................................................12-14

12.4.6

Divide Register n (TMCCDRn) TMCCDR0 0xF020, TMCCDR1 0xF120, TMCCDR2 0xF220 ....12-15

12.4.7

Pulse Generator Mode Register n (TMPGMRn) TMPGMR0 0xF030, TMPGMR1 0xF130 ............12-16

12.4.8

Watchdog Timer Mode Register n (TMWTMRn) TMWTMR2 0xF240 ...........................................12-17

12.4.9

Timer Read Register n (TMTRRn) 0xF0F0, TMTRR0 0xF0F0,

TMTRR1 0xF1F0, TMTRR2 0xF2F0 ...............................................................................................12-18

13. Parallel I/O Port.....................................................................................................................................................13-1

13.1

Characteristics ..............................................................................................................................................13-1

13.2

Block Diagram..............................................................................................................................................13-1

13.3

Detailed Description .....................................................................................................................................13-2

13.3.1

Selecting PIO Pins ...............................................................................................................................13-2

13.3.2

General-purpose Parallel Port ..............................................................................................................13-2

13.4

Registers .......................................................................................................................................................13-2

13.4.1

PIO Output Data Register (PIODO) 0xF500 .......................................................................................13-3

13.4.2

PIO Input Data Register (PIODI) 0xF504 ...........................................................................................13-4

13.4.3

PIO Direction Control Register (PIODIR) 0xF508..............................................................................13-5

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