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TMPR4925 bảng dữ liệu(PDF) 97 Page - Toshiba Semiconductor |
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TMPR4925 bảng dữ liệu(HTML) 97 Page - Toshiba Semiconductor |
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97 / 590 page ![]() Chapter 5 Configuration Register 5-7 Bits Mnemonic Field Name Description 10:9SELTMR[1:0] Select TIMER Select TIMER (Initial value: 00, R/W) Select TIMER Pins as PIO[20:19] pin. Please refer to “3.3 Pin Multiplexing” about setting. 8 SELDONE Select DMADONE* Select DMADONE* (Initial value: 0, R/W) Select DMADONE* as PIO[0] pin. Please refer to “3.3 Pin Multiplexing” about setting. 7:4 Reserved 3 SELACLC Select ACLC Select ACLC (Initial value: 0, R/W) Select ACLC function as PIO[17:12] pin. Please refer to “3.3 Pin Multiplexing” about setting. 2SELNAND Select NAND Interface Select NAND Interface (Initial value: 0, R/W) Select NAND Flash Memory function as PIO[17:12] pin. Please refer to “3.3 Pin Multiplexing” about setting. 1:0 SELDMA Select DMA Select DMA (Initial value: 00, R/W) Select DMA ch1,0 signals (DMAACK, DMAREQ) function as PIO[4:1] pin. Please refer to “3.3 Pin Multiplexing” about setting. Figure 5.2.3 Pin Configuration Register (PCFG) (2/2) |
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