TMPR4925 datasheet(48/590 Pages) TOSHIBA

48 / 590 page

Chapter 1 Features

1-2

1.2

Features

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TX49/H2 core with an integrated IEEE 754-compliant FPU for single- and double-precision operations

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4-channel SDRAM Controller (32 bit/80 MHz) and support SyncFlash® memory

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6-channel External Bus Controller (including 2-slot PCMCIA Interface)

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NAND Flash Controller

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32-bit PCI Controller (33 MHz)

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4-channel Direct Memory Access (DMA) Controller

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2-channel Serial I/O Port

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Parallel I/O Port (up to 32-bit)

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SPI (Serial Peripheral Interface)

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CHI (high-speed serial Concentration Highway Interface)

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Interrupt Controller

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3-channel Timer/Counter and 44-bit up-counter RTC

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AC-Link Controller

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PCMCIA Interface (2-slot)

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Supports selection between little endian and big endian modes

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Low power dissipation

The TX4925 operates with the 1.5 V core and the 3.3 V I/O, while supporting a low-power (Halt) mode.

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CPU maximum operating frequency: 200 MHz

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IEEE1149.1 (JTAG) support: Debug Support Unit (Enhanced JTAG)

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256-pin PBGA package

1.2.1

TX49/H2 Processor Core Features

The TX49/H2 is a high-performance 64-bit microprocessor core developed by Toshiba.

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64-bit operation

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32-, 64-bit integer general purpose registers

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32-bit physical address space and 64-bit virtual address space

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Optimized 5-stage pipeline

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Instruction Set

− MIPS I, II , III compatible ISA

− PREF (Prefetch) and MAC (Multiply/Accumulate) instructions.

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16k Byte Instruction Cache, and 16k Byte Data Cache

− 4-way set associative with lock function

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MMU (Memory Management Unit): 48-entry fully associative JTLB

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The on-chip FPU supports both single- and double-precision arithmetic, as specified in IEEE Std

754.

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On-chip 4-deep write buffer

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Enhanced JTAG debug feature

− Built-in Debug Support Unit (DSU)

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