TMPR4925 datasheet(239/590 Pages) TOSHIBA

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Chapter 9 SDRAM Controller

9-11

9.3.5

Bus Errors

The SDRAMC detects bus errors in the following situations:

•

Bus time-out occurs during Read or Write operation to the SDRAMC

If a bus error occurs when accessing the SDRAMC, then the SDRAMC will immediately abort

current operation. Then, the current SDRAM cycle will end, remaining SDRAMC operations will be

aborted, a Pre-charge All command will be issued to SDRAM, then the SDRAMC will return to the Idle

state.

9.3.6

Memory Read and Memory Write

The RAS* signal, CAS* signal, WE*, signal, ADDR[19:16], SADDR10, and ADDR[14:5] signal are

set up 1 cycle before the SDCS* signal is asserted in the case of the Read command, Write command,

Pre-charge command, or Mode Register Set command. The same set up time is observed even for active

commands if the Active Command Ready bit (SDCTR.DA) of the SDRAM Timing Register is set.

Figure 9.5.1 is a timing diagram of Single Read operation when the SDCTR.DA bit is cleared. Figure

9.5.2 is a timing diagram of Single Read operation when the SDCTR.DA bit is set.

Burst or Single Read operation is terminated by the Pre-charge Active Bank command. Burst or

Single Write operation is terminated by the Auto Pre-charge Command.

9.3.7

Slow Write Burst

When the Slow Write Burst bit (SDCTR.SWB) of the SDRAM Timing Register is cleared, the data

changes at each cycle during Burst Write operation (Figure 9.5.6). When the Slow Write Burst bit is set,

the data will change every other cycle (Figure 9.5.7).

When Slow Write Burst bit is set, it always operates as tRCD = 3tCK against all write access in no

relation with the value of RAS-CAS Delay bit (SDCTR.RCD) of SDRAM Timing Register. When slow

write burst is invalid, the value of RAS-CAS Delay bit is valid. During read access the value of RAS-

CAS Delay bit is valid in no relation with Slow Write Burst bit setup.

9.3.8

Clock Feedback

When performing Read access at fast rates like 80 MHz, there may be insufficient set up time if an

attempt to directly latch Read data with the internal clock is made. With the TX4925, it is possible to

latch data using SDRAM clock SDCLKIN that is input from outside the chip. Please connect

SDCLKIN to one of the SDCLK[1:0] pins and the external source.

9.3.9

SyncFlash ®

SDRAMC supports SyncFlash Memory. This memory is drop-in compatible with SDRAM for reads

and require a special command sequence for writes and other control operations. The Low power

consumption function is some different from SDRAM. Please refer 9.3.4 in detail.

A write to SFCMD register performs a Load Command Register (LCR) Cycle that is the first cycle of

SyncFlash memory command sequences to the SyncFlash device. The SyncFlash are fully supported in

16-bit mode for reads and writes (programming) with one exception. In order to read the “Device ID”

or “Device protect bit” using the Read Device Configuration LCR operation, the Memory Width field

for SyncFlash channel should be briefly set to 32-bit mode (SDCCRn.MW = 0). The relevant data will

be on the lower data bus, Data[15:0]. This allows the SDRAMC to correctly generate the odd address

necessary to read these SyncFlash configuration registers. All other LCR commands and reads and

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