TMPR4925 datasheet(241/590 Pages) TOSHIBA

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Chapter 9 SDRAM Controller

9-13

9.4.1

SDRAM Channel Control Register (SDCCR0)

0x8000 (ch. 0)

(SDCCR1)

0x8004 (ch. 1)

(SDCCR2)

0x8008 (ch. 2)

(SDCCR3)

0x800C (ch. 3)

AM[31:27]

R/W

: Type

0x1FC/0x000

0x0

: Initial

value

987

6543

210

AM[26:21]

Reserved

R/W

R/W : Type

0x00

000

0000

000

: Initial

value

Bits

Mnemonic

Field Name

Description

31:21

BA[31:21]

Base Address

Base Address (Initial value: (0x1FC & (ADDR[8:6]==000)/0x000, R/W)

Specifies the base address. The upper 11 bits [31:21] of the physical address are

compared to the value of this field.

(Note)

When ADDR[8:6] is 000b: 0x1FC (select SyncFlash as the Boot memory)

For all other ADDR[8:6] values: 0x000

20:10

AM[31:21]

Address Mask

Address Mask (Initial value: 0x000, R/W)

Sets the valid bits for address comparison according to the base address.

0: Bits of the corresponding BA field are compared.

1: Bits of the corresponding BA field are not compared.

Channel Enable

Enable (Initial value: (ADDR[8:6]==000)/0, R/W)

Specifies whether to enable a channel.

If ADDR[8:6] are 000 during the boot sequence to select SyncFlash as the boot

memory, the value in channel 0 become 1.

0: Disable

1: Enable

Memory Type

Memory Type (Initial value: (ADDR[8:6]==000)/0, R/W)

Specifies whether SDRAM or SynvFlash.

If ADDR[8:6] are 000 during the boot sequence to select SyncFlash as the boot

memory, the value in channel 0 become 1.

0: SDRAM

1: SyncFlash

Registered DIMM

Registered DIMM (Initial value: 0, R/W)

Specifies whether the SDRAM connected to the channel is Registered memory.

0: Disable Registered memory

1: Enable Registered memory



Reserved

Note: this bit is always set to “0” (Initial value: 0, R/W)

5:4

Row Size

Row Size (Initial value: ((-ADDR[5], ADDR[2]) & (ADDR[8:6]==000))/00, R/W)

Specifies the row size.

If ADDR[8:6] are 000 during the boot sequence to select SyncFlash as the boot

memory, the value of ADDR[5,2] during the boot sequence are set in these bits.

00: 2048 Rows (11 bits)

01: 4096 Rows (12 bits)

10: 8192 Rows (13 bits)

11: Reserved

(Note)

When ADDR[8:6] is 000b: Up to ADDR[5], ADDR[2] (select SyncFlash as

the Boot memory) For all other ADDR[8:6] values: 00

Figure 9.4.1 SDRAM Channel Control Register (1/2)

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