TMPR4925 datasheet(231/590 Pages) TOSHIBA

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Chapter 9 SDRAM Controller

9-3

9.3

Detailed Explanation

9.3.1

Supported SDRAM Configurations

This controller supports the SDRAM Configurations listed below in Table 9.3.1.

The MW field of the SDRAM Channel Control Register (SDCCRn) can be used to separately set the

data bus width for each channel to either 32 bits or 16 bits.

DATA[15:0] and DQM[1:0] are used when using a 16-bit data bus. DQM[3:2] output High.

DATA[31:16] output an undefined value when DATA[15:0] become the output, but enter the High-Z

state when DATA[15:0] are the input. When in the Big Endian Mode, first external access of the upper

half word (bits 31:16) of the internal data bus is performed, then external access of the lower half word

(bits 15:0) is performed. When in the Little Endian Mode, first external access of the lower half word

(bits 15:0) is performed, then external access of the upper half word (bits 31:16) is performed. When

using a 16-bit data bus, two external access will always be performed even when accessing less than 16

bits of data.

The maximum memory capacity per channel when a 32-bit data bus is configured is 512 MBytes

when using 8 512-Mbit SDRAMs with a 4-bit data bus. The total maximum memory capacity is 2

GBytes when totaling up the four channels.

Table 9.3.1 Supported SDRAM Configurations

SDRAM Configuration

Row Address (bit)

Column Address (bit)

Remarks

1 M

× 16

2 M

× 811

16 Mbit

2-bank

4 M

× 4

See Note

2 M

× 32

2 M

× 32

4 M

× 16

4 M

× 16

8 M

× 813

2-bank

16 M

× 4

See Note

2 M

× 32

4 M

× 16

8 M

× 812

64 Mbit

4-bank

16 M

× 4

See Note

4 M

× 32

8 M

× 16

16 M

× 812

128 Mbit

4-bank

32 M

× 4

See Note

8 M

× 32

16 M

× 16

32 M

× 813

256 Mbit

4-bank

64 M

× 4

See Note

32 M

× 16

64 M

× 813

512 Mbit

4-bank

128 M

× 4

See Note

Note1: The SDRAM Controller logic-wise does support these configurations, but please design

carefully since the memory bus load will be large.

Note2: With this composition, since the memory size of one channel is 512 Mbyte, if the memory area

is mapped from physical address 0, it will overlap with the address area which is used for ROM

area of boot vector.

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