S75WS256NDFBAWMB datasheet(155/216 Pages) SPANSION

155 / 216 page

February 17, 2005 S75WS-N-00_A0

S75WS256Nxx Based MCPs

153

Advance

Information

29.4 Mixed-Mode Operation

The device can support a combination of synchronous Read and asynchronous Write operations

when the BCR is configured for synchronous operation. The asynchronous Write operation re-

quires that the clock (CLK) remain static (High or Low) during the entire sequence. The ADV#

signal can be used to latch the target address, or it can remain Low during the entire Write oper-

ation. CE# can remain Low when transitioning between mixed-mode operations with fixed latency

enabled. Note that the tCKA period is the same as a Read or Write cycle. This time is required to

ensure adequate refresh. Mixed-mode operation facilitates a seamless interface to legacy burst

mode Flash memory controllers. See Figure 34.18, Asynchronous Write Followed by Burst Read

(timing diagram).

29.5 Wait Operation

The Wait output on a CellularRAM device is typically connected to a shared, system-level Wait sig-

nal (Figure 29.6). The shared Wait signal is used by the processor to coordinate transactions with

multiple memories on the synchronous bus.

Once a Read or Write operation has been initiated, Wait goes active to indicate that the Cellular-

RAM device requires additional time before data can be transferred. For Read operations, Wait will

remain active until valid data is output from the device. For Write operations, Wait will indicate to

the memory controller when data will be accepted into the CellularRAM device. When Wait tran-

sitions to an inactive state, the data burst will progress on successive clock edges.

CE# must remain asserted during Wait cycles (Wait asserted and Wait configuration BCR[8] = 1).

Bringing CE# High during Wait cycles may cause data corruption. (Note that for BCR[8] = 0, the

actual Wait cycles end one cycle after Wait de-asserts, and for row boundary crossings, start one

cycle after the Wait signal asserts.)

When using variable initial access latency (BCR[14] = 0), the Wait output performs an arbitration

role for Read or Write operations launched while an on-chip refresh is in progress. If a collision

occurs, the Wait pin is asserted for additional clock cycles until the refresh has completed

(Figure 29.7 and Figure 29.8). When the refresh operation has completed, the Read or Write op-

eration will continue normally.

Wait is also asserted when a continuous Read or Write burst crosses the boundary between 128-

word rows. The Wait assertion allows time for the new row to be accessed, and permits any pend-

ing refresh operations to be performed.

Wait will be asserted but should be ignored during asynchronous Read and Write, and page Read

operations.

29.6 LB#/UB# Operation

The LB# enable and UB# enable signals support byte-wide data transfers. During Read opera-

tions, the enabled byte(s) are driven onto the DQs. The DQs associated with a disabled byte are

put into a High-Z state during a Read operation. During Write operations, any disabled bytes will

Figure 29.6 Wired or Wait Configuration

CellularRAM

External

Pull-Up/

Pull-Down

Resistor

Processor

READY

Other

Device

WAIT

Other

Device

WAIT

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