S75WS256NDFBAWMB datasheet(27/216 Pages) SPANSION

27 / 216 page

February 17, 2005 S75WS-N-00_A0

S75WS256Nxx Based MCPs

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Information

Starting address: whether the address is divisible by four (where A[1:0] is 00). A divisible-

by-four address incurs the least number of additional wait states that occur after the initial

word. The number of additional wait states required increases for burst operations in which

the starting address is one, two, or three locations above the divisible-by-four address (i.e.,

where A[1:0] is 01, 10, or 11).

Boundary crossing: There is a boundary at every 128 words due to the internal architecture

of the device. One additional wait state must be inserted when crossing this boundary if the

memory bus is operating at a high clock frequency. Please refer to the tables below.

Clock frequency: the speed at which the device is expected to burst data. Higher speeds

require additional wait states after the initial word for proper operation.

In all cases, with or without latency, the RDY output indicates when the next data is available to

be read.

Tables 8.2 – 8.6 reflect wait states required for S29WS256/128/064N devices. Refer to the Con-

figuration Register table (CR11 – CR14) and timing diagrams for more details.

Table 8.2 Address Latency (S29WS256N)

Word

Wait States

Cycle

x ws

1 ws

x ws

1 ws

x ws

1 ws

Table 8.3 Address Latency (S29WS128N/S29WS064N)

Word

Wait States

Cycle

5, 6, 7 ws

1 ws

5, 6, 7 ws

1 ws

5, 6, 7 ws

1 ws

Table 8.4 Address/Boundary Crossing Latency (S29WS256N @ 80/66 MHz)

Word

Wait States

Cycle

7, 6 ws

1 ws

7, 6 ws

1 ws

7, 6 ws

1 ws

7, 6 ws

1 ws

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