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S75WS256NDFBAWMB bảng dữ liệu(PDF) 15 Page - SPANSION |
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S75WS256NDFBAWMB bảng dữ liệu(HTML) 15 Page - SPANSION |
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15 / 216 page ![]() February 17, 2005 S75WS-N-00_A0 S75WS256Nxx Based MCPs 13 Advance Information 3 Input/Output Descriptions and Logic Symbol Table 3.1 identifies the input and output package connections provided on the device. Table 3.1 Input/Output Descriptions Symbol Description Amax – A0 Address Inputs (Common) DQ15 - DQ0 Data Inputs/Outputs OE# Output Enable input WE# Write Enable input VSS Ground NC No Connect; not connected internally. RDY Ready output. Indicates the status of the Burst read. (Flash) CLK Clock input. In burst mode, after the initial word is output, subsequent active edges of CLK increment the internal address counter. Should be at VIL or VIH while in asynchronous mode. (Common) AVD# Address Valid input. Indicates to device that the valid address is present on the address inputs. (Flash) F-RST# Hardware reset input. F-WP# Hardware write protect input. At VIL, disables program and erase functions in the four outermost sectors. Should be at VIH for all other conditions. F-ACC Accelerated input. At VHH, accelerates programming; automatically places device in unlock bypass mode. At VIL, disables all program and erase functions. Should be at VIH for all other conditions. R-CE# Chip-enable input for pSRAM F-CE# Chip-enable input for Flash. Asynchronous relative to CLK for Burst Mode. F1-CE# Chip-enable input for Flash 1. F2-CE# Chip-enable input for Flash 2. F3-CE# Chip-enable input for Flash 3. R-CRE Control Register Enable . (pSRAM – CellularRAM only) F-VCC Flash 1.8 Volt-only single power supply. R-VCC pSRAM Power Supply. R-UB# Upper Byte Control. (pSRAM) R-LB# Lower Byte Control . Note: R-CRE is only present in CellularRAM-compatible pSRAM. DQ15 – DQ0 16 Amax – A0 CE# F-WP F-ACC F-CE# R-CE# OE# WE# F-RST# AVD# R-UB# R-LB# R-CRE RDY CLK (See Note) |
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