S75WS256NDFBAWMB datasheet(26/216 Pages) SPANSION

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S75WS256Nxx Based MCPs

S75WS-N-00_A0 February 17, 2005

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Inf o rmation

8.3

Synchronous (Burst) Read Mode and Configuration Register

When a series of adjacent addresses needs to be read from the device (in order from lowest to

highest address), the synchronous (or burst read) mode can be used to significantly reduce the

overall time needed for the device to output array data. After an initial access time required for

the data from the first address location, subsequent data is output synchronized to a clock input

provided by the system.

The device offers both continuous and linear methods of burst read operation, which are dis-

cussed in sections 8.3.1, 8.3.2, and 8.3.3.

Since the device defaults to asynchronous read mode after power-up or a hardware reset, the

configuration register must be set to enable the burst read mode. Other Configuration Register

settings include the number of wait states to insert before the initial word (tIACC) of each burst

access, the burst mode in which to operate, and when RDY indicates data is ready to be read.

Prior to entering the burst mode, the system should first determine the configuration register set-

tings (and read the current register settings if desired via the Read Configuration Register

command sequence), and then write the configuration register command sequence. See 8.3.4

and Table 13.1 for further details.

Figure 8.1 Synchronous/Asynchronous State Diagram

The device outputs the initial word subject to the following operational conditions:

tIACC specification: the time from the rising edge of the first clock cycle after addresses are

latched to valid data on the device outputs.

Configuration register setting CR13–CR11: the total number of clock cycles (wait states)

that occur before valid data appears on the device outputs. The effect is that tIACC is

lengthened.

The device outputs subsequent words tBACC after the active edge of each successive clock cycle,

which also increments the internal address counter. The device outputs burst data at this rate sub-

ject to the following operational conditions:

Power-up/

Hardware Reset

Asynchronous Read

Mode Only

Synchronous Read

Mode Only

Set Burst Mode

Configuration Register

Command for

Synchronous Mode

(CR15 = 0)

Set Burst Mode

Configuration Register

Command for

Asynchronous Mode

(CR15 = 1)

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