S75WS256NDFBAWMB datasheet(153/216 Pages) SPANSION

153 / 216 page

February 17, 2005 S75WS-N-00_A0

S75WS256Nxx Based MCPs

151

Advance

Information

29.3 Burst Mode Operation

Burst mode operations enable High-speed synchronous Read and Write operations. Burst opera-

tions consist of a multi-clock sequence that must be performed in an ordered fashion. After CE#

goes Low, the address to access is latched on the rising edge of the next clock that ADV# is Low.

During this first clock rising edge, WE# indicates whether the operation is going to be a Read

(WE# = High, Figure 29.4) or Write (WE# = Low, Figure 29.5).

The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length

bursts consist of four, eight, or sixteen words. Continuous bursts have the ability to start at a

specified address and burst through the entire memory.

The latency count stored in the BCR defines the number of clock cycles that elapse before the

initial data value is transferred between the processor and CellularRAM device.

The Wait output asserts as soon as a burst is initiated, and de-asserts to indicate when data is to

be transferred into (or out of) the memory. Wait will again be asserted if the burst crosses a row

boundary. Once the CellularRAM device has restored the previous row's data and accessed the

next row, Wait will be deasserted and the burst can continue (see Figure 34.9).

To access other devices on the same bus without the timing penalty of the initial latency for a new

burst, burst mode can be suspended. Bursts are suspended by stopping CLK. CLK can be stopped

High or Low. If another device will use the data bus while the burst is suspended, OE# should be

taken High to disable the CellularRAM outputs; otherwise, OE# can remain Low. Note that the

Wait output will continue to be active, and as a result no other devices should directly share the

Wait connection to the controller. To continue the burst sequence, OE# is taken Low, then CLK is

restarted after valid data is available on the bus.

See How Extended Timings Impact CellularRAM™ Operation for restrictions on the maximum CE#

Low time during burst operations. If a burst suspension will cause CE# to remain Low for longer

than tCEM, CE# should be taken High and the burst restarted with a new CE# Low/ADV# low

cycle.

Figure 29.3 Page Mode Read Operation (ADV# Low)

CE#

OE#

WE#

ADDRESS

DATA

LB#/UB#

Don't Care

ADD[1]

ADD[2]

ADD[3]

tAA

D[0]

tAPA

D[1]

tAPA

D[2]

tAPA

D[3]

ADD[0]

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