S75WS256NDFBAWMB datasheet(151/216 Pages) SPANSION

151 / 216 page

February 17, 2005 S75WS-N-00_A0

S75WS256Nxx Based MCPs

149

Advance

Information

29 Bus Operating Modes

CellularRAM products incorporate a burst mode interface found on Flash products targeting low-

power, wireless applications. This bus interface supports asynchronous, page mode, and burst

mode Read and Write transfers. The specific interface supported is defined by the value loaded

into the BCR. Page mode is controlled by the refresh configuration register (RCR[7]).

29.1 Asynchronous Mode

CellularRAM products power up in the asynchronous operating mode. This mode uses the industry

standard SRAM control bus (CE#, OE#, WE#, LB#/ UB#). Read operations (Figure 29.1) are ini-

tiated by bringing CE#, OE#, and LB#/UB# Low while keeping WE# High. Valid data will be driven

out of the I/Os after the specified access time has elapsed. Write operations (Figure 29.2) occur

when CE#, WE#, and LB#/ UB# are driven Low. During asynchronous Write operations, the OE#

level is a don't care, and WE# will override OE#. The data to be written is latched on the rising

edge of CE#, WE#, or LB#/UB# (whichever occurs first). Asynchronous operations (page mode

disabled) can either use the ADV input to latch the address, or ADV can be driven Low during the

entire Read/Write operation.

During asynchronous operation, the CLK input must be held static (High or Low, no transitions).

Wait will be driven while the device is enabled and its state should be ignored.

Note: ADV must remain Low for page mode operation.

Figure 29.1 Read Operation (ADV# Low)

Data Valid

Address Valid

tRC = READ Cycle Time

CE#

OE#

WE#

ADDRESS

DATA

LB#/UB#

Don't Care

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