S75WS256NDFBAWMB datasheet(148/216 Pages) SPANSION

148 / 216 page

146

S75WS256Nxx Based MCPs

S75WS-N-00_A0 February 17, 2005

Ad van c e

Inf o rmation

Notes:

1. CLK may be High or Low, but must be static during synchronous Read, synchronous Write, burst suspend, and DPD modes; and to achieve

standby power during standby and active modes.

2. The Wait polarity is configured through the bus configuration register (BCR[10]).

3. When LB# and UB# are in select mode (Low), DQ[15:0] are affected. When only LB# is in select mode, DQ[7:0] are affected. When only

UB# is in the select mode, DQ[15:8] are affected.

4. The device will consume active power in this mode whenever addresses are changed.

5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.

6. VIN = VCCQ or 0V; all device balls must be static (unswitched) to achieve standby current.

7. DPD is maintained until RCR is reconfigured.

Table 27.2 Bus Operations—Asynchronous Mode

Mode

Power

Clk

(Note 1) ADV#

CE#

OE#

WE#

CRE

LB#/

UB#

Wait

(Note 2)

DQ[15:0]

(Note 3)Notes

Read

Active

Low-Z

Data-Out

Write

Active

LLL

Low-Z

Data-In

Standby

High-Z

5, 6

No Operation

Idle

Low-Z

4, 6

Configuration

Active

LHLH

Low-Z

High-Z

DPD

Deep

Power-down

High-Z

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