S75WS256NDFBAWMB datasheet(144/216 Pages) SPANSION

144 / 216 page

142

S75WS256Nxx Based MCPs

S75WS-N-00_00_A0 February 17, 2005

Data

Sheet

26 Erase and Programming Performance

Notes:

1. Typical program and erase times assume the following conditions: 25

°C, 1.8 V V

CC, 100,000 cycles typical. Additionally,

programming typically assumes a checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 1.65 V, 100,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed.

4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command.

See the Command Definitions table for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 100,000 cycles.

Parameter

Typ

(Note 1)

Max

(Note 2)

Unit

Comments

Sector Erase Time

256 Kword

VCC

220

Excludes 00h programming prior to

erasure (Note 4)

ACC

Chip Erase Time

VCC

308

616

ACC

262

524

Word Programming Time

VCC

<40

<400

µs

Excludes system level overhead

(Note 5)

ACC

<24

<240

Effective Word Programming

Time utilizing Program Write Buffer

VCC

<9.4

<94

µs

ACC

<60

Total 32-Word BufferProgramming Time

VCC

<300

<3000

µs

ACC

<192

<1920

Chip Programming Time (Note 3)

VCC

<314.6

<629.2

Excludes system level overhead

(Note 5)

ACC

<201.4

<402.6

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