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CYT4DNJBJS bảng dữ liệu(PDF) 109 Page - Infineon Technologies AG

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Giải thích chi tiết về linh kiện  TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual
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Datasheet
109
002-24601 Rev. *I
2023-02-14
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications
26.3
Reset specifications
Figure 26-3
Reset sequence
Table 26-4
XRES_L Reset
Spec ID Parameter
Description
Min
Typ
Max
Units
Details/conditions
XRES_L DC specifications
SID73
IIDD_XRES
IDD when XRES_L asserted
–
–
1.7
mA Typ: TA = 25 °C,
VDDD = 5 V, process typ (TT)
Max: TA = 105 °C,
VDDD = 5.5 V,
process worst (FF)
SID74
VIH
Input voltage high threshold
0.7 ×
VDDD
––
V
CMOS Input
SID75
VIL
Input voltage low threshold
–
–
0.3 ×
VDDD
V
CMOS Input
SID76
RPULLUP
Pull-up resistor
7
–
20
kΩ
SID77
CIN
Input capacitance
–
–
5
pF
SID78
VHYSXRES
Input voltage hysteresis
0.05 ×
VDDD
––
V
XRES_L AC specifications
SID70
tXRES_ACT
XRES_L deasserted to Active
transition time
–
–
265
µs Without boot runtime
Guaranteed by design
SID71
tXRES_PW
XRES_L pulse width
5
–
–
µs
SID72
tXRES_FT
Pulse suppression width
100
–
–
ns
ACTIVE
RESET
HV/LV reset
System clock
System reset
release
release
MODES
12
1:
SID68/68A/68B: Time from HV/LV reset release until CM0+ begins executing ROM boot
2:
SID80A/80B: ROM boot code operation
3:
SID81A/81B/81C: Flash boot code operation
4:
User code operation
34



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