CYT4DNJBJS datasheet(113/209 Pages) INFINEON

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Datasheet

113

002-24601 Rev. *I

2023-02-14

TRAVEO™ T2G 32-bit Automotive MCU

Based on Arm® Cortex®-M7 dual

Electrical specifications

SID657I VOH5

Output voltage HIGH

level

DDIO_SMC – 0.5

–

IOL = –52 mA

CFG_OUT/DRIVE_SEL<1:0> =

0b00

CFG_OUT/SLOW<0:0> = 0b1

–40 °C  TA  –30 °C

VDDIO_SMC ≥ 4.5 V

SID658A RPD

Pull-down resistance

100

kΩ

SID659A RPU

Pull-up resistance

100

kΩ

SID659B VOUT

Mid range voltage

level

2.45

–

2.55

CFG/DRIVE_MODE<2:0> = 0b001

SID660A VIH_CMOS

Input voltage HIGH

threshold in CMOS

mode

0.7 × V

DDIO_SMC

––

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b0

CFG_IN/VTRIP_SEL<0:0> = 0b0

SID661A VIH_TTL

Input voltage HIGH

threshold in TTL

mode

2.0

–

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b0

CFG_IN/VTRIP_SEL<0:0> = 0b1

SID662A VIH_AUTO

Input voltage HIGH

threshold in AUTO

mode

0.8 × V

DDIO_SMC

––

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b1

CFG_IN/VTRIP_SEL<0:0> = 0b0

4.5 V  VDDIO_SMC  5.5 V

SID663A VIL_CMOS

Input voltage LOW

threshold in CMOS

mode

–

0.3 ×

DDIO_SMC

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b0

CFG_IN/VTRIP_SEL<0:0> = 0b0

SID664A VIL_TTL

Input voltage LOW

threshold in TTL

mode

––

0.8

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b0

CFG_IN/VTRIP_SEL<0:0> = 0b1

SID665A VIL_AUTO

Input voltage LOW

threshold in AUTO

mode

–

0.5 ×

DDIO_SMC

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b1

CFG_IN/VTRIP_SEL<0:0> = 0b0

4.5 V  VDDIO_SMC  5.5 V

SID666A VHYST_CMOS Hysteresis in CMOS

mode

0.05 ×

DDIO_SMC

––

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b0

CFG_IN/VTRIP_SEL<0:0> = 0b0

SID668A VHYST_AUTO Hysteresis in AUTO

mode

0.05 ×

DDIO_SMC

––

CFG_IN_AU-

TOLVL/VTRIP_SEL<0:0>= 0b1

CFG_IN/VTRIP_SEL<0:0> = 0b0

4.5 V  VDDIO_SMC  5.5 V

SID669A CIN

Input pin

capacitance

––

pF Test condition: 10/100MHz

SID670A IIL

Input leakage current

–2

–

µA VDDIO_SMC = VDDD = 5.5 V, VSS < VI <

VDDIO_SMC

–40 °C  TA  105 °C

This is valid for the pin which do

not have ADC input functionality.

SID673A tR_F_FAST

Rise time or fall time

(10% to 90% of

DDIO_SMC)

1–

ns 5 mA drive strength

20-pF load,

CFG_OUT/DRIVE_SEL<1:0> =

0b01, CFG_OUT/SLOW<0:0> =

0b0, guaranteed by design

SID674A tR_F_FAST

Rise time or fall time

(10% to 90% of

DDIO_SMC)

1–

ns 2 mA drive strength

10-pF load,

CFG_OUT/DRIVE_SEL<1:0> =

0b10, CFG_OUT/SLOW<0:0> =

0b0, guaranteed by design

SID675A tR_F_FAST

Rise time or fall time

(10% to 90% of

DDIO_SMC)

1–

ns 1 mA drive strength

6-pF load,

CFG_OUT/DRIVE_SEL<1:0> =

0b11, CFG_OUT/SLOW<0:0> =

0b0, guaranteed by design

Table 26-5

I/O specifications (continued)

Spec ID Parameter

Description

Min

Typ

Max

Units

Details/conditions

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