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CYT4DNJBJS bảng dữ liệu(PDF) 107 Page - Infineon Technologies AG |
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CYT4DNJBJS bảng dữ liệu(HTML) 107 Page - Infineon Technologies AG |
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107 / 209 page  Datasheet 107 002-24601 Rev. *I 2023-02-14 TRAVEO™ T2G 32-bit Automotive MCU Based on Arm® Cortex®-M7 dual Electrical specifications SID68C tHIB_ACT Release time from HV reset (POR, BOD, OVD, OCD, WDT, Hibernate wakeup, or XRES_L) until CM0+ begins executing ROM boot – – 650 µs Without boot runtime with max. 103.4 µF smoothing capacitor per SID41, no FPD/MIPI filter connected Guaranteed by Design SID68D tHIB_ACT Release time from HV reset (POR, BOD, OVD, OCD, WDT, Hibernate wakeup, or XRES_L) until CM0+ begins executing ROM boot – – 1040 µs Without boot runtime with max. 103.4 µF smoothing capacitor per SID41 + max. 5x11 µF FPD/MIPI filter caps Guaranteed by Design SID68A tLVR_ACT Release time from LV reset (Fault, Internal system reset, MCWDT, or CSV) during Active/Sleep until CM0+ begins executing ROM boot 8– 10 µs Without boot runtime. Guaranteed by design SID68B tLVR_DS Release time from LV reset (Fault, or MCWDT) during DeepSleep until CM0+ begins executing ROM boot –– 15 µs Without boot runtime. Guaranteed by design SID79 tHIBWAKE- UP_PW Pulse width for wakeup from Hibernate mode on HIBERANTE_WAKEUP pins 90 – – ns Guaranteed by design SID80A tRB_N ROM boot startup time or wakeup time from hibernate in NORMAL protection state – – 1700 µs FAST_BOOT = 1, CM0+ clocked at 100 MHz SID80B tRB_S ROM boot startup time or wakeup time from hibernate in SECURE protection state – – 2300 µs FAST_BOOT = 1, CM0+ clocked at 100 MHz SID81A tFB Flash boot startup time or wakeup time from hibernate in NORMAL/SECURE protection state – – 190 µs FAST_BOOT = 1, TOC2_FLAGS = 0x2CF, CM0+ clocked at 100 MHz, Listen window = 0 ms SID81B tFB_A Flash boot with app authentication time in NORMAL/SECURE protection state – – 5000 µs FAST_BOOT = 1, TOC2_FLAGS = 0x24F, CM0+ clocked at 100 MHz, Listen window = 0 ms, Public key exponent e = 0x010001, APP size is 64 KB with the last 256 bytes being a digital signature in RSASSA-PKCS1-v1.5 Valid for RSA2K. SID81C tFB_B Flash boot with app authentication time in NORMAL/SECURE protection state – – 8150 µs FAST_BOOT = 1, TOC2_FLAGS = 0x24F, CM0+ clocked at 100 MHz, Listen window = 0 ms, Public key exponent e = 0x010001, APP size is 64 KB with the last 384 bytes being a digital signature in RSASSA-PKCS1-v1.5 Valid for RSA3K. Regulator specifications SID600 VCCD Internal regulator core supply voltage (transient range) 1.05 1.1 1.15 V Table 26-3 DC specifications, CPU current, and transition time specifications (continued) All specifications are valid for –40°C TA 105°C and for 2.7 V to 5.5 V except where noted. Spec ID Parameter Description Min Typ Max Units Details/conditions |
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